List of x86 instructions

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.
The x86 instruction set has been extended several times, introducing wider registers and datatypes as well as new functionality.

x86 integer instructions

Below is the full 8086/8088 instruction set of Intel. These instructions are also available in 32-bit mode, in which they operate on 32-bit registers and values instead of their 16-bit counterparts. The updated instruction set is grouped according to architecture and is referred to as x86 and x86-64.

Original 8086/8088 instructions

This is the original instruction set. In the 'Notes' column, r means register, m means memory address and imm means immediate.

In- struc- tion	Meaning	Notes	Opcode
	ASCII adjust AL after addition	used with unpacked binary-coded decimal
	ASCII adjust AX before division	8086/8088 datasheet documents only base 10 version of the AAD instruction, but any other base will work. Later Intel's documentation has the generic form too. NEC V20 and V30 always use base 10, and ignore the argument, causing a number of incompatibilities
	ASCII adjust AX after multiplication	Only base 10 version is documented, see notes for AAD
	ASCII adjust AL after subtraction
	Add with carry	`r += ;` `m += ;`	...,...,
	Add	`r += r/m/imm;` `m += r/imm;`	...,...,
	Logical AND	`r &= r/m/imm;` `m &= r/imm;`	...,...,
	Call procedure		,,,
	Convert byte to word	`AX = AL ; sign extended`
	Clear carry flag	`CF = 0;`
	Clear direction flag	`DF = 0;`
	Clear interrupt flag	`IF = 0;`
	Complement carry flag	`CF = !CF;`
	Compare operands	`r - r/m/imm;` `m - r/imm;`	...,...,
	Compare bytes in memory. May be used with a or prefix to test and repeat the instruction times.
	Compare words. May be used with a or prefix to test and repeat the instruction times.
	Convert word to doubleword
	Decimal adjust AL after addition
	Decimal adjust AL after subtraction
	Decrement by 1		...,,
	Unsigned divide	`AX = DX:AX / r/m;` resulting `DX = remainder` `AL = AX / r/m;` resulting `AH = remainder`	,
	Used with floating-point unit		..
	Enter halt state
	Signed divide	`AX = DX:AX / r/m;` resulting `DX = remainder` `AL = AX / r/m;` resulting `AH = remainder`	,
	Signed multiply in One-operand form	`DX:AX = AX * r/m;` `AX = AL * r/m`	,
	Input from port	`AL = port;` `AL = port;` `AX = port;` `AX = port;`	,,,
	Increment by 1		...,,
	Call to interrupt		,
	Call to interrupt if overflow
	Return from interrupt
	Jump if condition		...
	Jump if CX is zero	for ECX instead of CX in 32 bit mode.
	Jump		...,,
	Load FLAGS into AH register
	Load DS:r with far pointer	`r = m; DS = 2 + m;`
	Load Effective Address
	Load ES:r with far pointer	`r = m; ES = 2 + m;`
	Assert BUS LOCK# signal
	Load string byte. May be used with a prefix to repeat the instruction times.
	Load string word. May be used with a prefix to repeat the instruction times.
/	Loop control		...
	Move	`r = r/m/imm;` `m = r/imm;` `r/m = sreg;` `sreg = r/m;`	...,,
	Move byte from string to string. May be used with a prefix to repeat the instruction times.	.
	Move word from string to string. May be used with a prefix to repeat the instruction times.
	Unsigned multiply	`DX:AX = AX * r/m;` `AX = AL * r/m;`	,
	Two's complement negation		...
	No operation	opcode equivalent to
	Negate the operand, logical NOT		...
	Logical OR	`r ∣= r/m/imm;` `m ∣= r/imm;`	...,...,
	Output to port	`port = AL;` `port = AL;` `port = AX;` `port = AX;`	,,,
	Pop data from stack	`r/m/sreg = *SP++;`	,,,...,
	Pop FLAGS register from stack	`FLAGS = *SP++;`
	Push data onto stack		,,,,...,
	Push FLAGS onto stack
	Rotate left		...,...
	Rotate right		...,...
	Repeat MOVS/STOS/CMPS/LODS/SCAS		,
	Return from procedure	Not a real instruction. The assembler will translate these to a RETN or a RETF depending on the memory model of the target system.
	Return from near procedure		,
	Return from far procedure		,
	Rotate left		...,...
	Rotate right		...,...
	Store AH into FLAGS
	Shift Arithmetically left	`r/m <<= 1;` `r/m <<= CL;`	...,...
	Shift Arithmetically right	`r/m >>= 1;` `r/m >>= CL;`	...,...
	Subtraction with borrow	`r -= ;` `m -= ;` alternative 1-byte encoding of is available via undocumented SALC instruction	...,...,
	Compare byte string. May be used with a or prefix to test and repeat the instruction times.
	Compare word string. May be used with a or prefix to test and repeat the instruction times.
	Shift left	Same opcode as SAL, since logical left shifts are equal to arithmetical left shifts.	...,...
	Shift right		...,...
	Set carry flag	`CF = 1;`
	Set direction flag	`DF = 1;`
	Set interrupt flag	`IF = 1;`
	Store byte in string. May be used with a prefix to repeat the instruction times.
	Store word in string. May be used with a prefix to repeat the instruction times.
	Subtraction	`r -= r/m/imm;` `m -= r/imm;`	...,...,
	Logical compare	`r & r/m/imm;` `m & r/imm;`	,,,,,
	Wait until not busy	Waits until BUSY# pin is inactive
	Exchange data	A spinlock typically uses xchg as an atomic operation..	,,...
	Table look-up translation	behaves like
	Exclusive OR	`r ^+= r/m/imm;` `m ^= r/imm;`	...,...,

Added in specific processors

Added with 80186">Intel 80186">80186/80188">Intel 80188">80188

New instructions and instruction forms added in the Intel 80186 and 80188. Also present in the NEC V20/V30 processors and their successors.

Added with [80286]

The new instructions added in 80286 add support for x86 protected mode. Some but not all of the instructions are available in real mode as well.

Added with [80386]

The 80386 added support for 32-bit operation to the x86 instruction set. This was done by widening the general-purpose registers to 32 bits and introducing the concepts of OperandSize and AddressSize – most instruction forms that would previously take 16-bit data arguments were given the ability to take 32-bit arguments by setting their OperandSize to 32 bits, and instructions that could take 16-bit address arguments were given the ability to take 32-bit address arguments by setting their AddressSize to 32 bits.
The default OperandSize and AddressSize to use for each instruction is given by the D bit of the segment descriptor of the current code segment - D=0 makes both 16-bit, D=1 makes both 32-bit. Additionally, they can be overridden on a per-instruction basis with two new instruction prefixes that were introduced in the 80386:66h: OperandSize override. Will change OperandSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1.67h: AddressSize override. Will change AddressSize from 16-bit to 32-bit if CS.D=0, or from 32-bit to 16-bit if CS.D=1.
The 80386 also introduced the two new segment registers FS and GS as well as the x86 control, debug and test registers.
The new instructions introduced in the 80386 can broadly be subdivided into two classes:

Pre-existing opcodes that needed new mnemonics for their 32-bit OperandSize variants
New opcodes that introduced new functionality

For instruction forms where the operand size can be inferred from the instruction's arguments, new instruction mnemonics are not needed and not provided.

Added with [80486]

Instruction	Opcode	Description	Ring
`BSWAP r32`		Byte Order Swap. Usually used to convert between big-endian and little-endian data representations. For 32-bit registers, the operation performed is: r = \| \| \| ; Using `BSWAP` with a 16-bit register argument produces an undefined result.	rowspan="5"
`CMPXCHG r/m8,r8`		Compare and Exchange. If accumulator compares equal to first operand, then `EFLAGS.ZF` is set to 1 and the first operand is overwritten with the second operand. Otherwise, `EFLAGS.ZF` is set to 0, and first operand is copied into the accumulator. Instruction atomic only if used with `LOCK` prefix.	-
		Compare and Exchange. If accumulator compares equal to first operand, then `EFLAGS.ZF` is set to 1 and the first operand is overwritten with the second operand. Otherwise, `EFLAGS.ZF` is set to 0, and first operand is copied into the accumulator. Instruction atomic only if used with `LOCK` prefix.	-
`XADD r/m,r8`		eXchange and ADD. Exchanges the first operand with the second operand, then stores the sum of the two values into the destination operand. Instruction atomic only if used with `LOCK` prefix.	-
`XADD r/m,r16` `XADD r/m,r32`	`0F C1 /r`	eXchange and ADD. Exchanges the first operand with the second operand, then stores the sum of the two values into the destination operand. Instruction atomic only if used with `LOCK` prefix.	-
`INVLPG m8`		Invalidate the TLB entries that would be used for the 1-byte memory operand. Instruction is serializing.	rowspan="2"
`WBINVD`		Write Back and Invalidate Cache. Writes back all modified cache lines in the processor's internal cache to main memory and invalidates the internal caches.	-
`INVD`	`0F 08`	Invalidate Internal Caches. Modified data in the cache are not written back to memory, potentially causing data loss.

Added in P5">Pentium (original)">P5/P6">P6 (microarchitecture)">P6-class processors

Integer/system instructions that were not present in the basic 80486 instruction set, but were added in various x86 processors prior to the introduction of SSE.

Added as instruction set extensions

Added with [x86-64]

These instructions can only be encoded in 64 bit mode. They fall in four groups:

original instructions that reuse existing opcodes for a different purpose
original instructions with new opcodes
existing instructions extended to a 64 bit address size
existing instructions extended to a 64 bit operand size

Most instructions with a 64 bit operand size encode this using a REX.W prefix; in the absence of the REX.W prefix,
the corresponding instruction with 32 bit operand size is encoded. This mechanism also applies to most other instructions with 32 bit operand
size. These are not listed here as they do not gain a new mnemonic in Intel syntax when used with a 64 bit operand size.

Instruction	Encoding	Meaning	Ring
`CDQE`	`REX.W 98`	Sign extend EAX into RAX	rowspan="13"
`CQO`	`REX.W 99`	Sign extend RAX into RDX:RAX	-
`CMPSQ`	`REX.W A7`	CoMPare String Quadword	-
		CoMPare and eXCHanGe 16 Bytes. Atomic only if used with LOCK prefix.	-
`IRETQ`	`REX.W CF`	64-bit Return from Interrupt	-
`JRCXZ rel8`	`E3 cb`	Jump if RCX is zero	-
`LODSQ`	`REX.W AD`	LoaD String Quadword	-
	`REX.W 63 /r`	MOV with Sign Extend 32-bit to 64-bit	-
`MOVSQ`	`REX.W A5`	Move String Quadword	-
`POPFQ`	`9D`	POP RFLAGS Register	-
`PUSHFQ`	`9C`	PUSH RFLAGS Register	-
`SCASQ`	`REX.W AF`	SCAn String Quadword	-
`STOSQ`	`REX.W AB`	STOre String Quadword	-
`SWAPGS`	`0F 01 F8`	Exchange GS base with KernelGSBase MSR
`UDB`	`D6`	Undefined instruction — will generate an invalid opcode exception in 64-bit mode.

Bit manipulation extensions

Bit manipulation instructions. For all of the VEX-encoded instructions defined by BMI1 and BMI2, the operand size may be 32 or 64 bits, controlled by the VEX.W bit – none of these instructions are available in 16-bit variants. The VEX-encoded instructions are not available in Real Mode and Virtual-8086 mode - other than that, the bit manipulation instructions are available in all operating modes on supported CPUs.

Added with Intel CET">Control-flow integrity#Intel Control-flow Enforcement Technology">Intel CET

Intel CET adds two distinct features to help protect against security exploits such as return-oriented programming: a shadow stack, and indirect branch tracking.

Added with XSAVE

The XSAVE instruction set extensions are designed to save/restore CPU extended state in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of state-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The EAX=0Dh CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits.

x87 floating-point instructions

The x87 coprocessor, if present, provides support for floating-point arithmetic. The coprocessor provides eight data registers, each holding one 80-bit floating-point value – these registers are organized as a stack, with the top-of-stack register referred to as "st" or "st", and the other registers referred to as st, st,...st. It additionally provides a number of control and status registers, including "PC" and "RC". Not all of the arithmetic instructions provided by x87 obey PC and RC.

Other instructions

x86 also includes discontinued instruction sets which are no longer supported by Intel and AMD, and [|undocumented] instructions which execute but are not officially documented.

Undocumented x86 instructions

The x86 CPUs contain undocumented instructions which are implemented on the chips but not listed in some official documents. They can be found in various sources across the Internet, such as Ralf Brown's Interrupt List and at
Some of these instructions are widely available across many/most x86 CPUs, while others are specific to a narrow range of CPUs.

Undocumented x87 instructions

Mnemonics	Opcodes	Description	Status
`FENI`, `FENI8087_NOP`	`DB E0`	FPU Enable Interrupts	Documented for the Intel 80287. Present on all Intel x87 FPUs from 80287 onwards. For FPUs other than the ones where they were introduced on, they act as `NOP`s. These instructions and their operation on modern CPUs are commonly mentioned in later Intel documentation, but with opcodes omitted and opcode table entries left blank. The opcodes are, however, recognized by Intel XED.
`FDISI`, `FDISI8087_NOP`	`DB E1`	FPU Disable Interrupts	Documented for the Intel 80287. Present on all Intel x87 FPUs from 80287 onwards. For FPUs other than the ones where they were introduced on, they act as `NOP`s. These instructions and their operation on modern CPUs are commonly mentioned in later Intel documentation, but with opcodes omitted and opcode table entries left blank. The opcodes are, however, recognized by Intel XED.
`FSETPM`, `FSETPM287_NOP`	`DB E4`	FPU Set Protected Mode	Documented for the Intel 80287. Present on all Intel x87 FPUs from 80287 onwards. For FPUs other than the ones where they were introduced on, they act as `NOP`s. These instructions and their operation on modern CPUs are commonly mentioned in later Intel documentation, but with opcodes omitted and opcode table entries left blank. The opcodes are, however, recognized by Intel XED.
		"Reserved by Cyrix" opcodes	These opcodes are listed as reserved opcodes that will produce "unpredictable results" without generating exceptions on at least Cyrix 6x86, 6x86MX, MII, MediaGX, and AMD Geode GX/LX. Their actual operation is not known, nor is it known whether their operation is the same on all of these CPUs.