X86 debug register

On the x86 architecture, a debug register is a register used by a processor for program debugging. There are six debug registers, named DR0...DR7, with DR4 and DR5 as obsolete synonyms for DR6 and DR7. The debug registers allow programmers to selectively enable various debug conditions associated with a set of four debug addresses.
Two of these registers are used to control debug features. These registers are accessed by variants of the MOV instruction. A debug register may be either the source operand or destination operand. The debug registers are privileged resources; the MOV instructions that access them can only be executed at privilege level zero. An attempt to read or write the debug registers when executing at any other privilege level causes a general protection fault.

DR0 to DR3

Each of these registers contains the linear address associated with one of four breakpoint conditions. Each breakpoint condition is further defined by bits in DR7.
The debug address registers are effective whether or not paging is enabled. The addresses in these registers are linear addresses. If paging is enabled, the linear addresses are translated into physical addresses by the processor's paging mechanism. If paging is not enabled, these linear addresses are the same as physical addresses.
Note that when paging is enabled, different tasks may have different linear-to-physical address mappings. When this is the case, an address in a debug address register may be relevant to one task but not to another. For this reason the x86 has both global and local enable bits in DR7. These bits indicate whether a given debug address has a global or local relevance.

DR6 - Debug status

The debug status register permits the debugger to determine which debug conditions have occurred. When the processor detects an enabled debug exception, it will set the corresponding bits of this register before entering the debug exception handler.

Bits	Abbreviation	Description
0	B0	Breakpoint #0 Condition Detected
1	B1	Breakpoint #1 Condition Detected
2	B2	Breakpoint #2 Condition Detected
3	B3	Breakpoint #3 Condition Detected
10:4
11	BLD	Cleared to 0 by the processor for Bus Lock Trap exceptions. On processors that don't support Bus Lock Trap exceptions, bit 11 of DR6 is a read-only bit, acting in the same way as bits 10:4.
12	BK, SMMS	SMM or ICE mode entered. Reserved and read as 0 on all later processors.
13	BD	Debug Register Access Detected.
14	BS	Single-Step execution
15	BT	Task Switch breakpoint. Occurs when a task switch is done with a TSS that has the T bit set.
16	RTM	Cleared to 0 by the processor for debug exceptions inside RTM transactions, set to 1 for all debug exceptions outside transactions. On processors without TSX, bit 16 of DR6 is a read-only bit, acting in the same way as bits 31:17.
31:17
63:32

DR7 - Debug control

The debug control register is used to selectively enable the four address breakpoint conditions, and to specify the type and size of each of the four breakpoints. There are two levels of enabling: the local and global levels. The local enable bits are automatically reset by the processor at every task switch to avoid unwanted breakpoint conditions in the new task. The global enable bits are not reset by a task switch; therefore, they can be used for conditions that are global to all tasks.

DR4 and DR5

Not real registers. On processors that support the CR4.DE bit, their behaviour is controlled by CR4.DE:

CR4.DE=0 : DR4 and DR5 alias to DR6 and DR7, respectively.
CR4.DE=1 : accessing DR4/5 results in #UD exception.

On processors without CR4.DE, the behaviour is officially undefined - usually, DR4/5 are aliased to DR6/7, but exceptions exist and have been used for CPU detection.