Comparison of instruction set architectures
An instruction set architecture is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an implementation. An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost ; because the ISA serves as the interface between software and hardware, software that has been written or compiled for an ISA can run on different implementations of the same ISA. This has enabled binary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in computing today.
An ISA defines everything a machine language programmer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported data types, what state there is and their semantics, the instruction set, and the input/output model.
Data representation
In the early decades of computing, there were computers that used binary, decimal and even ternary. Contemporary computers are almost exclusively binary.Characters are encoded as strings of bits or digits, using a wide variety of character sets; even within a single manufacturer there were character set differences.
Integers are encoded with a variety of representations, including sign-magnitude, ones' complement, two's complement, offset binary, nines' complement and ten's complement.
Similarly, floating-point numbers are encoded with a variety of representations for the sign, exponent and mantissa. In contemporary machines IBM hexadecimal floating-point and IEEE 754 floating point have largely supplanted older formats.
Addresses are typically unsigned integers generated from a combination of fields in an instruction, data from registers and data from storage; the details vary depending on the architecture.
Bits
s are often described as n-bit architectures. In the first three quarters of the 20th century, n was often 12, 18, 24, 30, 36, 48 or 60. In the last third of the 20th century, n was often 8, 16, or 32, and in the 21st century, n is often 16, 32 or 64, but other sizes have been used. This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the instruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the Z80, MC68000, and the IBM System/360. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles. On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the IBM System/360 Model 30, have smaller internal data paths, while others, such as the 360/195, have larger internal data paths.The external databus width is not used to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. IBM's PowerPC 604 has a 64-bit bus but only 32-bit registers. The System/360 processors, and some early 32-bit microprocessors such as the Motorola 68000, have 24-bit addresses.
The bit width of instructions in an architecture is not necessarily the bit width of the architecture. For example, instructions in System/360, the PDP-11 architecture, the VAX architecture, and the x86 architecture are variable-length. Initial versions of SuperH had fixed-length 16-bit instructions in spite of having a 32-bit architecture, while later versions had both 16-bit and 32-bit instructions.
Digits
In the first three quarters of the 20th century, word-oriented decimal computers typically had 10-digit words with a separate sign, using all ten digits in integers and using two digits for exponents in floating point numbers.Endianness
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several 8-bit architectures are little-endian. Most RISC architectures were originally big-endian, but many are now configurable as either.Endianness only applies to processors that allow individual addressing of units of data that are smaller than some of the data formats.
Instruction formats
Opcodes
In some architectures, an instruction has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the IBM System/370, byte 0 is the opcode but when byte 0 is a then byte 1 selects a specific instruction, e.g., is store clock. On some instruction set architectures, one or more opcode prefixes are used to alter the subsequent opcode or expand the number of opcodes.Operands
Addressing modes
Architectures typically allow instructions to include some combination of operand addressing modes:;Direct
;Immediate
;Indexed
;Indirect
;Truncated
;Base-displacement
;autoincrement/autodecrement
Vector processors have offered additional modes unique to element-based operations.
Number of operands
The number of operands is one of the factors that may give an indication about the performance of the instruction set.A three-operand architecture will allow
A := B + C
to be computed in one instruction
ADD B, C, A
A two-operand architecture will allow
A := A + B
to be computed in one instruction
ADD B, A
but requires that
A := B + C
be done in two instructions
MOVE B, A
ADD C, A
Encoding length
As can be seen in the table below some instructions sets keep to a very simple fixed encoding length, and other have variable-length. Usually it is RISC architectures that have fixed encoding length and CISC architectures that have variable length, but not always.Instruction sets
The table below compares basic information about instruction set architectures.Notes:
- Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. The column "Registers" only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program counter. Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register windows; for those architectures, the count indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.
- In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "load–store", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register, with the possible exceptions of memory locking instructions for atomic operations.
- In the "Endianness" column, "Bi" means that the endianness is configurable.
| Bits | Version | Max # operands | Type | Design | Registers | Instruction encoding | Branch evaluation | Extensions | Open | Royalty free | |||
| 6502 | 8 | 1975 | 1 | Register–Memory | CISC | 3 | Variable | Condition register | Little | ||||
| 6800 | 8 | 1974 | 1 | Register–Memory | CISC | 3 | Variable | Condition register | Big | ||||
| 6809 | 8 | 1978 | 1 | Register–Memory | CISC | 4 | Variable | Condition register | Big | ||||
| 680x0 | 32 | 1979 | 2 | Register–Memory | CISC | 8 data and 8 address | Variable | Condition register | Big | ||||
| 8080 | 8 | 1974 | 2 | Register–Memory | CISC | 7 | Variable | Condition register | Little | ||||
| 8051 | 32 | 1980 | 1 | Register–Register | CISC | Variable | Compare and branch | Little | |||||
| x86 | 16, 32, 64 | v4 | 1978 | 2 3 4 | Register–Memory | CISC | Variable | Condition code | Little | x87, IA-32, MMX, 3DNow!, SSE, SSE2, PAE, x86-64, SSE3, SSSE3, SSE4, BMI, AVX, AES, FMA, XOP, F16C, AMX | |||
| Alpha | 64 | 1992 | 3 | Register–Register | RISC | 32 | Fixed | Condition register | Bi | ,,, | |||
| ARC | 16/32/64 | ARCv3 | 1996 | 3 | Register–Register | RISC | 16 or 32 including SP user can increase to 60 | Variable | Compare and branch | Bi | APEX User-defined instructions | ||
| ARM/A32 | 32 | ARMv1–v9 | 1983 | 3 | Register–Register | RISC | Fixed | Condition code | Bi | NEON, Jazelle,, TrustZone, | |||
| Thumb/T32 | 32 | ARMv4T-ARMv8 | 1994 | 3 | Register–Register | RISC | Thumb: Fixed , Thumb-2: Variable | Condition code | Bi | NEON, Jazelle,, TrustZone, | |||
| Arm64/A64 | 64 | v8.9-A/v9.4-A, Armv8-R | 2011 | 3 | Register–Register | RISC | 32 | Fixed , Variable | Condition code | Bi | SVE and SVE2 | ||
| AVR instruction set|AVR] | 8 | 1997 | 2 | Register–Register | RISC | 32 16 on "reduced architecture" | Variable | Condition register, skip conditioned on an I/O or general purpose register bit, compare and skip | Little | ||||
| AVR32 | 32 | Rev 2 | 2006 | 2–3 | RISC | 15 | Variable | Big | Java virtual machine | ||||
| Blackfin | 32 | 2000 | 3 | Register–Register | RISC | 2 accumulators 8 data registers 8 pointer registers 4 index registers 4 buffer registers | Variable | Condition code | Little | ||||
| CDC Upper 3000 series | 48 | 1963 | 3 | Register–Memory | CISC | 48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous | Variable | Multiple types of jump and skip | Big | ||||
| CDC 6000 Central Processor (CP) | 60 | 1964 | 3 | Register–Register | 24 | Variable | Compare and branch | Compare/Move Unit | |||||
| CDC 6000 Peripheral Processor (PP) | 12 | 1964 | 1 or 2 | Register–Memory | CISC | 1 18-bit A register, locations 1–63 serve as index registers for some instructions | Variable | Test A register, test channel | additional Peripheral Processing Units | ||||
| Crusoe | 32 | 2000 | 1 | Register–Register | VLIW | Variable | Condition code | Little | |||||
| Elbrus 2000 | 64 | v6 | 2007 | 1 | Register–Register | VLIW | 8–64 | 64 | Condition code | Little | Just-in-time dynamic translation: x87, IA-32, MMX, SSE, SSE2, x86-64, SSE3, AVX | ||
| DLX | 32 | 1990 | 3 | Register–Register | RISC | 32 | Fixed | Condition register | Big | ||||
| eSi-RISC | 16/32 | 2009 | 3 | Register–Register | RISC | 8–72 | Variable | Compare and branch and condition register | Bi | User-defined instructions | |||
| iAPX 432 | 32 | 1981 | 3 | Stack machine | CISC | 0 | Variable | ||||||
| Itanium | 64 | 2001 | Register–Register | EPIC | 128 | Fixed | Condition register | Bi | Intel Virtualization Technology | ||||
| LoongArch | 32, 64 | 2021 | 4 | Register–Register | RISC | 32 | Fixed | Little | |||||
| M32R | 32 | 1997 | 3 | Register–Register | RISC | 16 | Variable | Condition register | Bi | ||||
| m88k | 32 | 1988 | 3 | Register–Register | RISC | 32 | Fixed | Compare and branch | Big | ||||
| Mico32 | 32 | 2006 | 3 | Register–Register | RISC | 32 | Fixed | Compare and branch | Big | User-defined instructions | |||
| MIPS | 64 | 6 | 1981 | 1–3 | Register–Register | RISC | 4–32 | Fixed | Condition register | Bi | MDMX, MIPS-3D | ||
| MMIX | 64 | 1999 | 3 | Register–Register | RISC | 256 | Fixed | Condition register | Big | ||||
| Nios II | 32 | 2000 | 3 | Register–Register | RISC | 32 | Fixed | Condition register | Little | Soft processor that can be instantiated on an Altera FPGA device | |||
| Nova | 16 | 1969 | 2 | Register–Register | CISC | 4 | Fixed | Skip | - | ||||
| NS320xx | 32 | 1982 | 5 | Memory–Memory | CISC | 8 | Variable Huffman coded, up to 23 bytes long | Condition code | Little | BitBlt instructions | |||
| OpenRISC | 32, 64 | 1.4 | 2000 | 3 | Register–Register | RISC | 16 or 32 | Fixed | Condition code | Bi | |||
| PA-RISC | 64 | 2.0 | 1986 | 3 | Register–Register | RISC | 32 | Fixed | Compare and branch | Big → Bi | MAX | ||
| PDP-5 PDP-8 | 12 | 1963 | Register–Memory | CISC | 1 accumulator 1 multiplier quotient register | Fixed | Condition register Test and branch | EAE | |||||
| PDP-11 | 16 | 1970 | 2 | Memory–Memory | CISC | 8 | Variable | Condition code | Little | Extended Instruction Set, Floating Instruction Set, Floating Point Processor, Commercial Instruction Set | |||
| POWER instruction set architecture|POWER], PowerPC, Power ISA | 32/64 | 3.1 | 1990 | 3. FMA, LD/ST-Update | Register–Register | RISC | 32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register | Fixed , Variable | Condition code, Branch-Counter auto-decrement | Bi | AltiVec, APU, VSX, Cell, Floating-point, Matrix Multiply Assist | Licensed by OPF | Only if licensed |
| RISC-V | 32, 64, 128 | 20250508 | 2010 | 3 | Register–Register | RISC | 32 | Variable | Compare and branch | Little | |||
| RX | 64/32/16 | 2000 | 3 | Memory–Memory | CISC | 4 integer + 4 address | Variable | Compare and branch | Little | ||||
| S+core | 16/32 | 2005 | RISC | Little | |||||||||
| SPARC | 64 | OSA2017 | 1985 | 3 | Register–Register | RISC | 32 | Fixed | Condition code | Big → Bi | VIS | ||
| SuperH | 32 | 1994 | 2 | Register–Register Register–Memory | RISC | 16 | Fixed , Variable | Condition code | Bi | ||||
| System/360 System/370 System/390 z/Architecture | 64 | 1964 | 2 3 4 | Register–Memory Memory–Memory Register–Register | CISC | 16 general 16 control 16 access 32 vector registers | Variable | Condition code, compare and branch, Branch-Counter auto-decrement | Big | ||||
| TMS320 C6000 series | 32 | 1983 | 3 | Register-Register | VLIW | 32 on C67x 64 on C67x+ | Fixed | Condition register | Bi | ||||
| Transputer | 32 | 1987 | 1 | Stack machine | MISC | 3 | Fixed | Compare and branch | Little | ||||
| VAX | 32 | 1977 | 6 | Memory–Memory | CISC | 16 | Variable | Condition code, compare and branch | Little | ||||
| Z80 | 8 | 1976 | 2 | Register–Memory | CISC | 17 | Variable | Condition register | Little |