Power ISA


Power ISA is a reduced instruction set computer instruction set architecture currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor.
Prior to version 3.0, the ISA is divided into several categories. Processors implement a set of these categories as required for their task. Different classes of processors are required to implement certain categories, for example a server-class processor includes the categories: Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.
Power ISA is a RISC load/store architecture. It has multiple sets of registers:
Instructions up to version 3.0 have a length of 32 bits, with the exception of the VLE subset that provides for higher code density for low-end embedded applications, and version 3.1 which introduced prefixing to create 64-bit instructions. Most instructions are triadic, i.e. have two source operands and one destination. Single- and double-precision IEEE 754 compliant floating-point operations are supported, including additional fused multiply–add and decimal floating-point instructions. There are provisions for single instruction, multiple data operations on integer and floating-point data on up to 16 elements in one instruction.
Power ISA has support for Harvard cache, i.e. split data and instruction caches, and support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. There is also support for both big and little-endian addressing with separate categories for moded and per-page endianness, and support for both 32-bit and 64-bit addressing.
Different modes of operation include user, supervisor and hypervisor.

Categories

The Power ISA specification is divided into five parts, called "books":
  • Book I – User Instruction Set Architecture covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like digital signal processors and the AltiVec extension.
  • Book II – Virtual Environment Architecture defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
  • Book III – Operating Environment Architecture includes exceptions, interrupts, memory management, debug facilities and special control functions. It is divided into two parts.
  • * Book III-S – Defines the supervisor instructions used for general-purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA.
  • * Book III-E – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
  • Book VLE – Variable Length Encoded Instruction Architecture defines alternative instructions and definitions from Books I–III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big-endian byte ordering.

    Compliancy

New in version 3 of the Power ISA is that implementations need not implement the entire specification to be compliant. The sprawl of instructions and technologies has made the complete specification unwieldy, so the OpenPOWER Foundation have decided to enable tiered compliancy.
These levels include optional and mandatory requirements. An implementation that is compliant at a lower level is allowed to have additional selected functions from higher levels and custom extensions. It is recommended that an option be provided to disable any added functions beyond the design's declared subset level.
A design must be compliant at its declared subset level to make use of the Foundation's protection regarding use of intellectual property, be it patents or trademarks. This is explained in the OpenPOWER EULA.
A compliant design must:
  • Support the Base architecture
  • And support at least one of the subsets
  • * SFS – Scalar Fixed-point Subset. 129 instructions. Basic fixed point and load/store instructions, which is really the Base architecture.
  • * SFFS – Scalar Fixed-point + Floating-point Subset. 214 instructions. Adding floating-point operations to the Base.
  • * LCS – Linux Compliancy Subset. 962 instructions. Intended for server grade Linux, adding features like 64-bit, optional SIMD/VSX, Radix MMU, little-endian mode and hypervisor support.
  • * ACS – AIX Compliancy Subset. 1099 instructions. Intended to run AIX, adding features like decimal and quad-precision floating point, big-endian mode and symmetric multiprocessing.
  • May include any of the features of the LCS and ACS as Optional or pick from the Always Optional features like matrix math and power management.
  • Optional features, if chosen, must be implemented in their entirety.
  • May include Custom extensions, specific to the implementation, implemented in the Architecture Sandbox. If the extension is general-purpose enough, the OpenPOWER Foundation asks that implementors submit it as a Request for Comments to the . Note that it is not strictly necessary to join the OpenPOWER Foundation to submit RFCs.
  • Much may be implemented in either hardware or firmware.

    EABI and Linux Compliancy discrepancy

The EABI specifications predate the announcement and creation of the Compliancy subsets.
Regarding the Linux Compliancy subset having VSX optional: in 2003–04, 64-bit EABI v1.9 made SIMD optional, but in July 2015, to improve performance for IBM POWER9 systems, SIMD was made mandatory in EABI v2.0. This discrepancy between SIMD being optional in the Linux Compliancy level but mandatory in EABI v2.0 cannot be rectified without considerable effort: backwards incompatibility for Linux distributions is not a viable option.

Specifications

Power ISA v.2.03

The specification for Power ISA v.2.03 is based on the former PowerPC ISA v.2.02 in POWER5+ and the Book E extension of the PowerPC specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
;Compliant cores
The specification for Power ISA v.2.04 was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the Book III-S part regarding virtualization, hypervisor functions, logical partitioning and virtual page handling.
;Compliant cores
  • All cores that comply with prior versions of the Power ISA
  • The PA6T core from P.A. Semi
  • Titan from AMCC

    Power ISA v.2.05

The specification for Power ISA v.2.05 was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to Book I and Book III-S, including significant enhancements such as decimal arithmetic and server hypervisor improvements.
;Compliant cores
  • All cores that comply with prior versions of the Power ISA
  • POWER6
  • PowerPC 476

    Power ISA v.2.06

The specification for Power ISA v.2.06 was released in February 2009, and revised in July 2010. It is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and e500-mc core. One significant new feature is vector-scalar floating-point instructions. Book III-E also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations.
The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features.
;Compliant cores
  • All cores that comply with prior versions of the Power ISA
  • POWER7
  • A2I
  • e500-mc
  • e5500
  • e6500

    Power ISA v.2.07

The specification for Power ISA v.2.07 was released in May 2013. It is based on Power ISA v.2.06 and includes major enhancements to logical partition functions, transactional memory, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities, along with AES and Galois Counter Mode, SHA-224, SHA-256, SHA-384 and SHA-512 cryptographic extensions and cyclic redundancy check algorithms.
The spec was revised in April 2015 to the Power ISA v.2.07 B spec.
;Compliant cores
  • All cores that comply with prior versions of the Power ISA
  • POWER8
  • A2O

    Power ISA v.3.0

The specification for Power ISA v.3.0 was released in November 2015. It is the first to come out after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of workloads and removes the server and embedded categories while retaining backwards compatibility and adds support for VSX-3 instructions. New functions include 128-bit quad-precision floating-point operations, a random number generator, hardware-assisted garbage collection and hardware-enforced trusted computing.
The spec was revised in March 2017 to the Power ISA v.3.0 B spec,
and revised again to v3.0C in May 2020. One major change from v3.0 to v3.0B is the removal of support for hardware assisted garbage collection.
The key difference between v3.0B and v3.0C is that the Compliancy Levels listed in v3.1 were also added to v3.0C.
;Compliant cores
  • All cores that comply with prior versions of the Power ISA
  • POWER9
  • OpenPOWER Microwatt
  • Libre-SOC is aiming for Embedded FP compliancy with Power ISA 3.0 only