ARM Cortex-M

Overview

License

Silicon customization

• SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller. When present, it also provides an additional configurable priority SysTick interrupt. Though the SysTick timer is optional for the M0/M0+/M1/M23, it is extremely rare to find a Cortex-M microcontroller without it. If a Cortex-M33/M35P/M52/M55/M85 microcontroller has the Security Extension option, then it optionally can have two SysTicks.
• Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address. In particular, individual bits can be set, cleared, or toggled from C/C++ without performing a read-modify-write sequence of instructions. Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.
• Memory Protection Unit : Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to sixteen different regions, each of which can be split further into equal-size sub-regions.
• Tightly-Coupled Memory : Low-latency SRAM that can be used to hold the call stack, RTOS control structures, interrupt data structures, interrupt handler code, and speed critical code. Other than CPU cache, TCM is the fastest memory in an ARM Cortex-M microcontroller. Since TCM isn't cached and accessible at the same speed as the processor and cache, it could be conceptually described as "addressable cache". There is an ITCM and a DTCM to allow a Harvard architecture processor to read from both simultaneously. The DTCM can't contain any instructions, but the ITCM can contain data. Since TCM is tightly connected to the processor core, DMA engines might not be able to access TCM on some implementations.

• Note: Most Cortex-M3 and M4 chips have bit-band and MPU. The bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit.
• Note: Software should validate the existence of each feature before attempting to use it.
• Note: Limited public information is available for the Cortex-M35P until its Technical Reference Manual is released.

• Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.
• Interrupts: 1 to 32, 1 to 240, 1 to 480.
• Wake-up interrupt controller: Optional.
• Vector Table Offset Register: Optional..
• Instruction fetch width: 16-bit only, or mostly 32-bit.
• User/privilege support: Optional.
• Reset all registers: Optional.
• Single-cycle I/O port: Optional..
• Debug Access Port : None, SWD, JTAG and SWD.
• Halting debug support: Optional.
• Number of watchpoint comparators: 0 to 2, 0 to 4.
• Number of breakpoint comparators: 0 to 4, 0 to 8.

  Instruction sets

• Note: Interrupt latency cycle count assumes: 1) stack located in zero-wait state RAM, 2) another interrupt function not currently executing, 3) Security Extension option doesn't exist, because it adds additional cycles. The Cortex-M cores with a Harvard computer architecture have a shorter interrupt latency than Cortex-M cores with a Von Neumann computer architecture.
• Note: The Cortex-M series includes three new 16-bit Thumb-1 instructions for sleep mode: SEV, WFE, WFI.
• Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit Thumb-1 instructions: CBZ, CBNZ, IT.
• Note: The Cortex-M0 / M0+ / M1 only include these 32-bit Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.
• Note: The Cortex-M0 / M0+ / M1 / M23 only has 32-bit multiply instructions with a lower-32-bit result, where as the Cortex-M3 / M4 / M7 / M33 / M35P includes additional 32-bit multiply instructions with 64-bit results. The Cortex-M4 / M7 include DSP instructions for,, multiplications.
• Note: The number of cycles to complete multiply and divide instructions vary across ARM Cortex-M core designs. Some cores have a silicon option for the choice of fast speed or small size, so cores have the option of using less silicon with the downside of higher cycle count. An interrupt occurring during the execution of a divide instruction or slow-iterative multiply instruction will cause the processor to abandon the instruction, then restart it after the interrupt returns.
• * Multiply instructions "32-bit result" Cortex-M0/M0+/M23 is 1 or 32 cycle silicon option, Cortex-M1 is 3 or 33 cycle silicon option, Cortex-M3/M4/M7/M33/M35P is 1 cycle.
• * Multiply instructions "64-bit result" Cortex-M3 is 3–5 cycles, Cortex-M4/M7/M33/M35P is 1 cycle.
• * Divide instructions Cortex-M3/M4 is 2–12 cycles, Cortex-M7 is 3–20 cycles, Cortex-M23 is 17 or 34 cycle option, Cortex-M33 is 2–11 cycles, Cortex-M35P is TBD.
• Note: Some Cortex-M cores have silicon options for various types of floating point units. The Cortex-M55 / M85 has an option for half-precision, the Cortex-M4 / M7 / M33 / M35P / M52 / M55 / M85 has an option for single-precision, the Cortex-M7 / M52 / M55 / M85 has an option for double-precision. When an FPU is included, the core is sometimes referred as "Cortex-MxF", where 'x' is the core variant, such as Cortex-M4F.

• Note: MOVW is an alias that means 32-bit "wide" MOV instruction.
• Note: B.W is a long-distance unconditional branch.
• Note: For Cortex-M1, WFE / WFI / SEV instructions exist, but execute as a NOP instruction.
• Note: The half-precision FPU instructions are valid in the Cortex-M52 / M55 / M85 only when the HP FPU option exists in the silicon.
• Note: The single-precision FPU instructions are valid in the Cortex-M4 / M7 / M33 / M35P / M52 / M55 / M85 only when the SP FPU option exists in the silicon.
• Note: The double-precision FPU instructions are valid in the Cortex-M7 / M52 / M55 / M85 only when the DP FPU option exists in the silicon.