PCI Express
PCI Express[], officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside computers. It is designed to replace older expansion bus standards such as PCI, PCI-X and AGP. Developed and maintained by the PCI-SIG, PCIe is commonly used to connect graphics cards, sound cards, Wi-Fi and Ethernet adapters, and storage devices such as solid-state drives and hard disk drives.
Compared to earlier standards, PCIe supports faster data transfer, uses fewer pins, takes up less space, and allows devices to be added or removed while the computer is running. It also includes better error detection and supports newer features like I/O virtualization for advanced computing needs.
PCIe connections are made through lanes, which are pairs of conductors that send and receive data. Devices can use one or more lanes depending on how much data they need to transfer. PCIe technology is also used in laptop expansion cards and in storage connectors such as M.2, U.2, and SATA Express.
Architecture
Conceptually, the PCI Express bus is a high-speed serial replacement of the older PCI/PCI-X bus. One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared parallel bus architecture, in which the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on point-to-point topology, with separate serial links connecting every device to the root complex. Because of its shared bus topology, access to the older PCI bus is arbitrated, and limited to one master at a time, in a single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the slowest peripheral on the bus. In contrast, a PCI Express bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.In terms of bus protocol, PCI Express communication is encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCI Express port. Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors ; PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express preserves backward compatibility with PCI; legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the PCI Express standard, though new PCI Express features are inaccessible.
The PCI Express link between two devices can vary in size from one to 16 lanes. In a multi-lane link, the packet data is striped across lanes, and peak data throughput scales with the overall link width. The [|lane] count is automatically negotiated during device initialization and can be restricted by either endpoint. For example, a single-lane PCI Express card can be inserted into a multi-lane slot, and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure itself to use fewer lanes, providing a failure tolerance in case bad or unreliable lanes are present. The PCI Express standard defines link widths of ×1, ×2, ×4, ×8, and ×16. Up to and including PCIe 5.0, ×12, and ×32 links were defined as well but virtually never used. This allows the PCI Express bus to serve both cost-sensitive applications where high throughput is not needed, and performance-critical applications such as 3D graphics, networking, and enterprise storage. Slots and connectors are only defined for a subset of these widths, with link widths in between using the next larger physical slot size.
As a point of reference, a PCI-X device and a PCI Express 1.0 device using four lanes have roughly the same peak single-direction transfer rate of 1064 MB/s. The PCI Express bus has the potential to perform better than the PCI-X bus in cases where multiple devices are transferring data simultaneously, or if communication with the PCI Express peripheral is bidirectional.
Interconnect
PCI Express devices communicate via a logical connection called an interconnect or link. A link is a point-to-point communication channel between two PCI Express ports allowing both of them to send and receive ordinary PCI requests and interrupts. At the physical level, a link is composed of one or more lanes. Low-speed peripherals use a single-lane link, while a graphics adapter typically uses a much wider and therefore faster 16-lane link.Lane
A lane is composed of two differential signaling pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or signal traces. Conceptually, each lane is used as a full-duplex byte stream, transporting data packets in eight-bit "byte" format simultaneously in both directions between endpoints of a link. Physical PCI Express links may contain 1, 4, 8 or 16 lanes. Lane counts are written with an "x" prefix, with ×16 being the largest size in common use. Lane sizes are also referred to via the terms "width" or "by" e.g., an eight-lane slot could be referred to as a "by 8" or as "8 lanes wide."For mechanical card sizes, see [|below].
Serial bus
The bonded serial bus architecture was chosen over the traditional parallel bus because of the inherent limitations of the latter, including half-duplex operation, excess signal count, and inherently lower bandwidth due to timing skew. Timing skew results from separate electrical signals within a parallel interface traveling through conductors of different lengths, on potentially different printed circuit board layers, and at possibly different signal velocities. Despite being transmitted simultaneously as a single word, signals on a parallel interface have different travel duration and arrive at their destinations at different times. When the interface clock period is shorter than the largest time difference between signal arrivals, recovery of the transmitted word is no longer possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz.A serial interface does not exhibit timing skew because there is only one differential signal in each direction within each lane, and there is no external clock signal since clocking information is embedded within the serial signal itself. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz range. PCI Express is one example of the general trend toward replacing parallel buses with serial interconnects; other examples include Serial ATA, USB, Serial Attached SCSI, FireWire, and RapidIO. In digital video, examples in common use are DVI, HDMI, and DisplayPort, but they were replacements for analog VGA, not for a parallel bus.
Multichannel serial design increases flexibility with its ability to allocate fewer lanes for slower devices.
Form factors
PCI Express add-in card
A PCI Express add-in card fits into a slot of its physical size or larger, but may not fit into a smaller PCI Express slot; for example, a ×16 card may not fit into a ×4 or ×8 slot. Some slots use open-ended sockets to permit physically longer cards and negotiate the best available electrical and logical connection.The number of lanes actually connected to a slot may also be fewer than the number supported by the physical slot size. An example is a ×16 slot that runs at ×4, which accepts any ×1, ×2, ×4, ×8 or ×16 card, but provides only four lanes. Its specification may read as "×16 " or "×16 ", while "mechanical @ electrical" notation is also common. The advantage is that such slots can accommodate a larger range of PCI Express cards without requiring motherboard hardware to support the full transfer rate. Standard mechanical sizes are ×1, ×4, ×8, and ×16. Cards using a number of lanes other than the standard mechanical sizes need to physically fit the next larger mechanical size.
The cards themselves are designed and manufactured in various sizes. For example, solid-state drives that come in the form of PCI Express cards often use HHHL and FHHL to describe the physical dimensions of the card. The concept of "full" and "half" heights and lengths are inherited from Conventional PCI.
The length levels beside full are not a PCIe standard, but only a manufacturer agreement. Half length provides sufficient space for a ×16 connector. Below that narrower data connectors need to be used.
These dimensions can be freely mixed and matched, but larger dimensions tend to co-occur.
There is a fixed distance of between the connector's key notch and the end of the card, which may be covered by an end plate with a screw-hole for installing onto the computer case. This fixed length ensures that cards do not protrude out of the chassis.
The slot spacing is exactly on ATX motherboards.
For further specifications of the slot, see #Physical layer below.
Non-standard video card form factors
Modern gaming video cards usually exceed the height as well as thickness specified in the PCI Express standard, due to the need for more capable and quieter cooling fans, as gaming video cards often emit hundreds of watts of heat. Modern computer cases are often wider to accommodate these taller cards, but not always. Since full-length cards are uncommon, modern cases sometimes cannot accommodate them. The thickness of these cards also typically occupies the space of 2 to 5 PCIe slots. In fact, even the methodology of how to measure the cards varies between vendors, with some including the metal bracket size in dimensions and others not.For instance, comparing three high-end video cards released in 2020: a Sapphire Radeon RX 5700 XT card measures 135 mm in height, which exceeds the PCIe standard height by 28 mm, another Radeon RX 5700 XT card by XFX measures 55 mm thick, taking up 3 PCIe slots, while an Asus GeForce RTX 3080 video card takes up two slots and measures 140.1mm × 318.5mm × 57.8mm, exceeding PCI Express's maximum height, length, and thickness respectively.