List of MIPS architecture processors

This is a list of processors that implement the MIPS instruction set architecture, sorted by year, process size, frequency, die area, and so on. These processors are designed by Imagination Technologies, MIPS Technologies, and others. It displays an overview of the MIPS processors with performance and functionality versus capabilities for the more recent MIPS Aptiv families.

MIPS Computer Systems/MIPS Technologies

MIPS version	Processor	Year	Process	Frequency	Transistors	Die area	Pin count	Power	Voltage	D. cache	I. cache	MMU	L2 cache	L3 cache	Features
MIPS I	R2000	1985	2000	8 to 16.67	0.11	80				64 external	64 external		none	none	5 stage pipelines, FPU: 2010
MIPS I	R3000	1988	1200	12 to 40	0.11	40	145, 172	4		32-256 external	32-256 external		0-1 MB external	none	same as R2000; FPU: 3010
MIPS II	R6000	1990		60 to 66						external	external		none	none	32-bit register size, 36-bit physical address, FPU
MIPS III	R4000	1991	800	100	1.35	213	179	15	5	8	8		128 KB to 4 MB external	none
MIPS III	R4400	1992	600	100 to 250	2.3	186	179	15	5, 3.3	16	16		128 KB to 4 MB external	none
MIPS III	R4200	1993	600	80	1.3	81	179	1.8-2.0	3.3	8	16		128 KB to 4 MB external	none	scalar design with a five-stage classic RISC pipeline
MIPS III	R4300i	1995	350	100 / 133		45	120	2.2	3.3					none
MIPS III	R4600	1994	640	100 / 133	2.2	77	179	4.6	5	16	16		512 KB external	none
MIPS III	R4650	1994	640	133 / 180	2.2	77	179	4.6	5	16	16		512 KB external	none
MIPS III	R4640	1995	640				179							none
MIPS III	R4700	1996	500	100 to 200	2.2		179			16	16		External	none
MIPS IV	R5000	1996	350	150 to 200	3.7	84	223	10	3.3	32	32		1 MB external	none
MIPS IV	RM7000	1998	250, 180, 130	250 to 600	18	91	304	10, 6, 3	3.3, 2.5, 1.5	16	16		256 KB internal	1 MB external
MIPS IV	R8000	1994	700	75 to 90	2.6	299	591	30	3.3	16	16		4 MB external	none	superscalar, up to 4 instructions per cycle
MIPS IV	R10000	1996	350, 250	150 to 250	6.7	350	599	30	3.3	32	32		512 KB – 16 MB external	none
MIPS IV	R12000	1998	350, 250	270 to 360	7.15	229	600	20	4	32	32		512 KB – 16 MB external	none	single-chip 4-issue superscalar
MIPS IV	R12000A	2000	180	400										none
MIPS IV	R14000	2001	130	500	7.2	204	527	17		32	32		512 KB – 16 MB external	none
MIPS IV	R14000A	2002	130	600				17		32	32			none
MIPS IV	R16000	2003	110	700 to 1000				20		64	64		512 KB – 16 MB external	none
MIPS IV	R16000A	2004	110	800 to 1000						64	64			none
MIPS IV	R18000	2001	130						1.2	32	32		1 MB	0-64 MB external, on-chip tag	was planned, but not manufactured
MIPS V	H1 "Beast"													none	was planned, but not manufactured
MIPS V	H2 "Capitan"													none	was planned, but not manufactured
MIPS32	4K	1999	180	167		2.5								none
MIPS32	4KE		90	420		1.2								none
MIPS32	24K	2003	130, 65, 40	400 750 1468		0.83				0 to 64	0 to 64		4–16 MB external	none
MIPS32	24KE	2003	130, 65, 40											none
MIPS32	34K	2006	90, 65, 40	500 1454										none
MIPS32	74K	2007	65	1110		2.5				0 to 64	0 to 64			none
MIPS32	1004K	2008	65	1100		4.7				8 to 64	8 to 64			none
MIPS32	M14K	2009	130	200										none	MicroMIPS
MIPS32	1074K	2010	40	1500										none
MIPS32	1074Kf	2010	40											none	Floating point
MIPS32	microAptiv	2012	90, 65							8 to 64	8 to 64			none
MIPS32	interAptiv	2012								4 to 64	4 to 64		up to 8 MB internal	none
MIPS32	proAptiv	2012								32 or 64	32 or 64		up to 8 MB internal	none
MIPS64	5K	1999
MIPS64	20K	2000
MIPS version	Processor	Year	Process	Frequency	Transistors	Die area	Pin count	Power	Voltage	D. cache	I. cache	MMU	L2 cache	L3 cache	Features

Imagination Technologies

MIPS Technologies was acquired 17 December 2012, by Imagination Technologies. Since then, the following processors have been introduced by Imagination Technologies.
Imagination Technologies sold MIPS processor rights to Tallwood MIPS Inc in 2017. MIPS Technologies was acquired by Wave Computing in 2018, where "MIPS operates as an IP licensing business unit".
The Warrior P-Class CPU was announced on 14 October 2013.
The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and MIPS64 release 6, and will come in three classes of performance and features:

'Warrior M-class': entry-level MIPS cores for embedded and microcontroller applications, a progression from the popular microAptiv family
'Warrior I-class': mid-range, feature-rich MIPS CPUs following on from the highly efficient interAptiv family. The I6400, with its 64-bit core, was launched September 2014.
'Warrior P-class': high-performance MIPS processors building on the proAptiv family

MIPS version

level

Processor

Year

Process

Frequency

Transistors

Die area

Pin count

Power

Voltage

D. cache