IBM z14
The z14 is a microprocessor made by IBM for their z14 mainframe computers, announced on July 17, 2017. Manufactured at GlobalFoundries' East Fishkill, New York fabrication plant. IBM stated that it is the world's fastest microprocessor by clock rate at 5.2 GHz, with a 10% increased performance per core and 30% for the whole chip compared to its predecessor the z13.
Description
The Processor Unit chip has an area of 696 mm2 and consists of 6.1 billion transistors. It is fabricated using GlobalFoundries' 14 nm FinFET silicon on insulator fabrication process, using 17 layers of metal and supporting speeds of 5.2 GHz, which is higher than its predecessor, the z13. The PU chip has 10 cores but can have 7–10 cores enabled depending on configuration. The z14 cores support two-way simultaneous multithreading for more applications than previously available.The PU chip is packaged in a single-chip module, which is the same as its predecessor, but a departure from previous designs which were mounted on large multi-chip modules. A computer drawer consists of six PU chips and one Storage Controller chip containing the L4 cache.
The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline. z14 has a cryptographic coprocessor, called CPACF, attached to each core, used for random number generation, hashing, encryption and decrypting and compression. Further enhancements include an optimization of the core's pipeline, doubling the on-chip caches, better branch prediction, a new decimal arithmetic SIMD engine designed to boost COBOL and PL/I code, a "guarded storage facility" that helps Java applications during garbage collection, and other enhancements that increase the cores' performance compared to the predecessors.
The instruction pipeline has an instruction queue that can fetch 6 instructions per cycle; and issue up to 10 instructions per cycle. Each core has a private 128 KB L1 instruction cache, a private 128 KB L1 data cache, a private 2 MB L2 instruction cache, and a private 4 MB L2 data cache. In addition, there is a 128 MB shared L3 cache implemented in eDRAM.
The z14 chip has on board multi-channel DDR4 RAM memory controller supporting a RAID-like configuration to recover from memory faults. The z14 also includes two GX bus as well as two new Gen 3 PCIe controllers for accessing host channel adapters and peripherals. The PU chips has three X-buses for communications to three neighboring PU chips and the SC chip.