DDR4 SDRAM


Double Data Rate 4 Synchronous Dynamic Random-Access Memory is a type of synchronous dynamic random-access memory with a high-bandwidth interface.
Released to the market in 2014, it is a variant of dynamic random-access memory, some of which have been in use since the early 1970s, and a higher-speed successor to the DDR2 and DDR3 technologies.
DDR4 is not compatible with any earlier type of random-access memory due to different signaling voltage and physical interface, besides other factors.
DDR4 SDRAM was released to the public market in Q2 2014, focusing on ECC memory, while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of Haswell-E processors that require DDR4 memory.

Features

The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higher data rate transfer speeds. The DDR4 standard allows for DIMMs of up to 64 GB in capacity, compared to DDR3's maximum of 16 GB per DIMM.
Unlike previous generations of DDR memory, prefetch has not been increased above the 8n used in DDR3; the basic burst size is eight 64-bit words, and higher bandwidths are achieved by sending more read/write commands per second. To allow this, the standard divides the DRAM banks into two or four selectable bank groups, where transfers to different bank groups may be done more rapidly.
Because power consumption increases with speed, the reduced voltage allows higher speed operation without unreasonable power and cooling requirements.
DDR4 RAM operates at a voltage of 1.2 V and supports frequencies between 800 and 1600 MHz. Compared to DDR3, which operates at 1.5 V with frequencies from 400 to 1067 MHz, DDR4 offers better performance and energy efficiency. DDR4 speeds are advertised as double the base clock rate due to its Double Data Rate nature, with common speeds including DDR4-2400 and DDR4-3200, and higher speeds like DDR4-4266 and DDR4-5000 available at a premium. Unlike DDR3, DDR4 does not have a low voltage variant; it consistently operates at 1.2 V. Additionally, DDR4 improves on DDR3 with a longer burst length of 16 and supports larger memory capacities, enhancing both performance and system flexibility.

Timeline

  • 2005: Standards body JEDEC began working on a successor to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007. The high-level architecture of DDR4 was planned for completion in 2008.
  • 2007: Some advance information was published in 2007, and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum. DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.
  • 2009: In February, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a 50 nm process.
  • 2010: Subsequently, further details were revealed at MemCon 2010, Tokyo, at which a presentation by a JEDEC director titled "Time to rethink DDR4" with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably or definitely delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.
  • 2011: In January, Samsung announced the completion and release for testing of a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data transfer rate of 2133 MT/s at 1.2 V, uses pseudo open drain technology and draws 40% less power than an equivalent DDR3 module.
In April, Hynix announced the production of 2 GB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm, adding that it anticipated commencing high volume production in the second half of 2012. Semiconductor processes for DDR4 were expected to transition to sub-30 nm at some point between late 2012 and 2014.
  • 2012: In May, Micron announced it was aiming at starting production in late 2012 of 30 nm modules. In July, Samsung announced that it would begin sampling the industry's first 16 GB registered dual inline memory modules using DDR4 SDRAM for enterprise server systems. In September, JEDEC released the final specification of DDR4.
  • 2013: DDR4 was expected to represent 5% of the DRAM market in 2013, and to reach mass market adoption and 50% market penetration around 2015; as of 2013, however, adoption of DDR4 had been delayed and it was no longer expected to reach a majority of the market until 2016 or later. The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2. In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4.
  • 2014: In April, Hynix announced that it had developed the world's first highest-density 128 GB module based on 8 Gbit DDR4 using 20 nm technology. The module works at 2133 MHz, with a 64-bit I/O, and processes up to 17 GB of data per second.
  • 2016: In April, Samsung announced that they had begun to mass-produce DRAM on a "10 nm-class" process, by which they mean the 1x nm node regime of 16 nm to 19 nm, which supports a 30% faster data transfer rate of 3,200 Mbit/s. Previously, a size of 20 nm was used.
  • 2020: DDR5 RAM was formally introduced by the JEDEC Solid State Technology Association in July 2020 as the successor to DDR4. JEDEC, a global leader in developing open standards for the microelectronics industry, spearheaded the development of DDR5 to address the growing demands for higher performance and efficiency in modern computing. The DDR5 standard builds on the advancements of DDR4 with notable improvements in bandwidth, efficiency, and capacity, offering a base data rate of 4800 MT/s and supporting higher speeds as the technology matures. DDR5 also features enhanced power management, increased burst length, and improved prefetch capabilities, making it suitable for a wide range of applications from high-performance gaming to data-intensive computing tasks.

    Market perception and adoption

In April 2013, a news writer at International Data Group an American technology research business originally part of IDCproduced an analysis of their perceptions related to DDR4 SDRAM. The conclusions were that the increasing popularity of mobile computing and other devices using slower but low-powered memory, the slowing of growth in the traditional desktop computing sector, and the consolidation of the memory manufacturing marketplace, meant that margins on RAM were tight.
As a result, the desired premium pricing for the new technology was harder to achieve, and capacity had shifted to other sectors. SDRAM manufacturers and chipset creators were, to an extent, "stuck between a rock and a hard place" where "nobody wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory if they are not going to get a premium", according to Mike Howard from iSuppli. A switch in consumer sentiment toward desktop computing and release of processors having DDR4 support by Intel and AMD could therefore potentially lead to "aggressive" growth.
Intel's 2014 Haswell roadmap, revealed the company's first use of DDR4 SDRAM in Haswell-EP processors.
AMD's Ryzen processors, revealed in 2016 and shipped in 2017, use DDR4 SDRAM.

Operation

DDR4 RAM operates with a primary supply voltage of 1.2 V and an auxiliary 2.5 V supply for wordline boosting. This contrasts with DDR3, which runs at 1.5 V and had lower voltage variants at 1.35 V introduced in 2013. DDR4 was introduced with a minimum transfer rate of 2133 MT/s, influenced by DDR3's nearing limit at similar speeds, and is expected to reach up to 4266 MT/s. Notable improvements in DDR4 include increased data transfer rates and enhanced efficiency. Early DDR4 samples, such as those from Samsung in January 2011, showed a CAS latency of 13 clock cycles, comparable to the DDR2 to DDR3 transition. Additionally, DDR4 features a longer burst length of 16, higher capacity support, and improved signal integrity with tighter pin spacing, slightly increased height, and increased thickness for better signal routing and performance.
Internal banks are increased to 16, with up to 8 ranks per DIMM.
Protocol changes include:
  • Parity on the command/address bus
  • Data bus inversion
  • CRC on the data bus
  • Independent programming of individual DRAMs on a DIMM, to allow better control of on-die termination.
Increased memory density is anticipated, possibly using TSV or other 3D stacking processes. The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC, with provision for up to dies. X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive".
Switched memory banks are also an anticipated option for servers.
In 2008, the book Wafer Level 3-D ICs Process Technology highlighted concerns about the increasing die area consumption due to non-scaling analog elements like charge pumps, voltage regulators, and additional circuitry. These components, including CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedance, and a greater need for sense amplifiers, have significantly increased bandwidth but at the cost of occupying more die area. Consequently, the proportion of die allocated to the memory array itself has decreased over time: from 70–78% for SDRAM and DDR1 to 47% for DDR2, 38% for DDR3, and potentially less than 30% for DDR4.
The specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gbit.
In addition to bandwidth and capacity variants, DDR4 modules can optionally implement:
  • ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC4-19200 ECC or PC4-19200E is a PC4-19200 module with ECC.
  • Registered RAM enhances signal integrity, which can improve clock rates and allow for higher physical slot capacity, by buffering signals electrically. This comes at the cost of an additional clock cycle of latency. These modules are identified by an "R" in their designation, such as PC4-19200R. Typically, modules with this designation are also ECC Registered, though the 'E' for ECC may not always be included in the designation. Conversely, non-registered RAM, also known as unbuffered RAM, is identified by a "U" in the designation. e.g. PC4-19200U.
  • Be Load reduced modules, which are designated by LR and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides larger overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.