Cell (processor)
The Cell Broadband Engine is a 64-bit reduced instruction set computer multi-core processor and microarchitecture developed by Sony, Toshiba, and IBM—an alliance known as "STI". It combines a general-purpose PowerPC core, named the Power Processing Element, with multiple specialized coprocessors, known as Synergistic Processing Elements, which accelerate tasks such as multimedia and vector processing.
The architecture was developed over a four-year period beginning in March 2001, with Sony reporting a development budget of approximately. Its first major commercial application was in Sony's PlayStation 3 home video game console, released in 2006. In 2008, a modified version of the Cell processor powered IBM's Roadrunner, the first supercomputer to sustain one petaFLOPS. Other applications include high-performance computing systems from Mercury Computer Systems and specialized arcade system boards.
Cell emphasizes memory coherence, power efficiency, and peak computational throughput, but its design presented significant challenges for software development. IBM offered a Linux-based software development kit to facilitate programming on the platform.
History
In mid-2000, Sony, Toshiba, and IBM formed the STI alliance to develop a new microprocessor. The STI Design Center opened in March 2001 in Austin, Texas. Over the next four years, more than 400 engineers collaborated on the project, with IBM contributing from eleven of its design centers.Initial patents described a configuration with four Power Processing Elements, each paired with eight Synergistic Processing Elements, for a theoretical peak performance of 1 teraFLOPS. However, only a scaled-down design—one PPE with eight SPEs—was ultimately manufactured.
Fabrication of the initial Cell chip began on a 90 nm SOI process. In March 2007, IBM transitioned production to a 65 nm process, followed by a 45 nm process announced in February 2008. Bandai Namco Entertainment used the Cell processor in its Namco System 357 and 369 arcade boards.
In May 2008, IBM introduced the PowerXCell 8i, a double-precision variant of the Cell processor, used in systems such as IBM's Roadrunner supercomputer, the first to achieve one petaFLOPS and the fastest until late 2009.
IBM ceased development of higher-core-count Cell variants in late 2009, but continued supporting existing Cell-based products.
Commercialization
On May 17, 2005, Sony confirmed the Cell configuration used in the PlayStation 3: one PPE and seven SPEs. To improve manufacturing yield, the processor is initially fabricated with eight SPEs. After production, each chip is tested, and if a defect is found in one SPE, it is disabled using laser trimming. This approach minimizes waste by utilizing processors that would otherwise be discarded. Even in chips without defects, one SPE is intentionally disabled to ensure consistency across units. Of the seven operational SPEs, six are available for developers to use in games and applications, while the seventh is reserved for the console's operating system. The chip operates at a clock speed of 3.2 GHz. Sony also used the Cell in its Zego high-performance media computing server.The PPE supports simultaneous multithreading and can execute two threads, while each active SPE supports one thread. In the PlayStation 3 configuration, the Cell processor supports up to nine threads.
On June 28, 2005, IBM and Mercury Computer Systems announced a partnership to use Cell processors in embedded systems for medical imaging, aerospace, and seismic processing, among other fields. Mercury use the full Cell processor with eight active SPEs. Mercury later released blade servers and PCI Express accelerator cards based on the architecture.
In 2006, IBM introduced the QS20 blade server, offering up to 410 gigaFLOPS per module in single-precision performance. The QS22 blade, based on the PowerXCell 8i, was used in IBM's Roadrunner supercomputer. On April 8, 2008, Fixstars Corporation released a PCI Express accelerator board based on the PowerXCell 8i.
Overview
The Cell Broadband Engine, or Cell as it is more commonly known, is a microprocessor intended as a hybrid of conventional desktop processors and more specialized high-performance processors, such as the NVIDIA and ATI graphics-processors. The longer name indicates its intended use, namely as a component in current and future online distribution systems; as such it may be utilized in high-definition displays and recording equipment, as well as HDTV systems. Additionally the processor may be suited to digital imaging systems and physical simulation. As used in the PlayStation 3, it has 250 million transistors.In a simple analysis, the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element , eight fully functional co-processors called the Synergistic Processing Elements, or SPEs, and a specialized high-bandwidth circular data bus connecting the PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB.
To achieve the high performance needed for mathematically intensive tasks, such as decoding/encoding MPEG streams, generating or transforming three-dimensional data, or undertaking Fourier analysis of data, the Cell processor marries the SPEs and the PPE via EIB to give access, via fully cache coherent DMA, to both main memory and to other external data storage. To make the best of EIB, and to overlap computation and data transfer, each of the nine processing elements is equipped with a DMA engine. Since the SPE's load/store instructions can only access its own local scratchpad memory, each SPE entirely depends on DMAs to transfer data to and from the main memory and other SPEs' local memories. A DMA operation can transfer either a single block area of size up to 16KB or a list of 2 to 2048 such blocks. One of the major design decisions in the architecture of Cell is the use of DMAs as a central means of intra-chip data transfer, with a view to enabling maximal asynchrony and concurrency in data processing inside a chip.
The PPE, which is capable of running a conventional operating system, has control over the SPEs and can start, stop, interrupt, and schedule processes running on the SPEs. To this end, the PPE has additional instructions relating to the control of the SPEs. Unlike SPEs, the PPE can read and write the main memory and the local memories of SPEs through the standard load/store instructions. The SPEs are not fully autonomous and require the PPE to prime them before they can do any useful work. As most of the "horsepower" of the system comes from the synergistic processing elements, the use of DMA as a method of data transfer and the limited local memory footprint of each SPE pose a major challenge to software developers who wish to make the most of this horsepower, demanding careful hand-tuning of programs to extract maximal performance from this CPU.
The PPE and bus architecture includes various modes of operation, giving different levels of memory protection, allowing areas of memory to be protected from access by specific processes running on the SPEs or the PPE.
Both the PPE and SPE are RISC architectures with a fixed-width 32-bit instruction format. The PPE contains a 64-bit general-purpose register set, a 64-bit floating-point register set, and a 128-bit Altivec register set. The SPE contains 128-bit registers only. These can be used for scalar data types ranging from 8-bits to 64-bits in size, or for SIMD computations on various integer and floating-point formats. System memory addresses for both the PPE and SPE are expressed as 64-bit values. Local store addresses internal to the SPU processor are expressed as a 32-bit word. In documentation relating to Cell, a "word" is always taken to mean 32 bits, a "doubleword" means 64 bits, and a "quadword" means 128 bits.
PowerXCell 8i
In 2008, IBM announced a revised variant of the Cell called the PowerXCell 8i, which is available in the blade server by IBM, QS22. The PowerXCell is manufactured on a 65 nm process, and adds support for up to 32 GB of slotted double data rate 2 memory, as well as dramatically improving double-precision floating-point performance on the SPEs from a peak of about 12.8 giga-floating point operations per second to 102.4 GFLOPS total for eight SPEs, which is the same peak performance as the NEC SX-9 vector processor released around the same time. The IBM Roadrunner supercomputer, the world's fastest during 2008–2009, consisted of 12,240 PowerXCell 8i processors, along with 6,562 AMD Opteron processors. The PowerXCell 8i powered super computers also dominated all of the top 6 "greenest" systems in the Green500 list, with highest MFLOPS/Watt ratio supercomputers in the world. Beside the QS22 and supercomputers, the PowerXCell processor is also available as an accelerator on a PCI Express card and is used as the core processor in the QPACE project.Since the PowerXCell 8i removed the RAMBUS memory interface, and added significantly larger DDR2 interfaces and enhanced SPEs, the chip layout had to be reworked, which resulted in both larger chip die and packaging.
Architecture
While the Cell chip can have a number of different configurations, the basic configuration is a multi-core chip composed of one "Power Processor Element" , and multiple "Synergistic Processing Elements". The PPE and SPEs are linked together by an internal high speed bus dubbed "Element Interconnect Bus".Power Processor Element (PPE)
The PPE is the PowerPC based, dual-issue in-order two-way simultaneous-multithreaded CPU core with a 23-stage pipeline acting as the controller for the eight SPEs, which handle most of the computational workload. PPE has limited out-of-order execution capabilities; it can perform loads out of order and has delayed execution pipelines. The PPE will work with conventional operating systems due to its similarity to other 64-bit PowerPC processors, while the SPEs are designed for vectorized floating point code execution. The PPE contains a 32 KiB level 1 instruction cache, a 32 KiB level 1 data cache, and a 512 KiB level 2 cache. The size of a cache line is 128 bytes in all caches. Additionally, IBM has included an AltiVec unit which is fully pipelined for single precision floating point, 32-bit Fixed Point Unit with 64-bit register file per thread, Load and Store Unit, 64-bit Floating-Point Unit, Branch Unit and Branch Execution Unit.PPE consists of three main units: Instruction Unit, Execution Unit, and vector/scalar execution unit. IU contains L1 instruction cache, branch prediction hardware, instruction buffers, and dependency checking logic. XU contains integer execution units and load-store unit. VSU contains all of the execution resources for FPU and VMX. Each PPE can complete two double-precision operations per clock cycle using a scalar fused-multiply-add instruction, which translates to 6.4 GFLOPS at 3.2 GHz; or eight single-precision operations per clock cycle with a vector fused-multiply-add instruction, which translates to 25.6 GFLOPS at 3.2 GHz.