NEAT chipset
The NEAT chipset is a
4 chip VLSI implementation of the control logic used in the IBM PC compatible PC/AT computers. It consists of the 82C211 CPU/Bus controller, 82C212 Page/Interleave and EMS Memory controller, 82C215 Data/Address buffer, and 82C206 Integrated Peripherals Controller. NEAT, official designation CS8221, was developed by Chips and Technologies.
History
The NEAT chipset descended from the first chipset that C&T had developed for IBM XT-compatible systems, which is based around the 82C100 "XT controller" chip. 82C100 incorporates the functionality of what had been, until its invention, discrete TTL chips on the XT's mainboard, namely:- 8284 clock generator
- 8288 bus controller
- 8254 Programmable Interval Timer
- 8255 parallel I/O interface
- 8259 Programmable Interrupt Controller
- 8237 DMA controller
- 8255 Programmable Peripheral Interface
- DRAM/SRAM controller
- XT Keyboard controller
- 82284 clock generator
- 82288 bus controller
- 8254 Programmable Interval Timer
- two 8259 Programmable Interrupt Controllers
- two 8237 DMA controllers
- 74LS612 Memory Mapper chip
- MC146818 NVRAM/RTC chip