A Background Calibration Technique to Control the Bandwidth of Digital PLLs
A Background Calibration Technique to Control the Bandwidth of Digital PLLs is a scholarly work, published in 2018 in ''IEEE Journal of Solid State Circuits''. The main subjects of the publication include digital control, jitter, Bandwidth extension, computer science, electronic engineering, transfer function, electromagnetic compatibility, bandwidth, PLL multibit, CMOS, phase-locked loop, phase noise, control theory, and engineering. The paper presents a technique to regulate the bandwidth of digital phase-locked loops (PLLs), where a fully digital automatic control circuit, running in background, is used to desensitize loop gain from analog parameters.