ARM C-series


The ARM C-series is a family of ARM architecture processor cores developed by Arm Holdings, introduced in 2025 as part of the Armv9.3 architecture. Designed for consumer and mobile devices, the C-series succeeds ARM's Cortex-A and Cortex-X naming scheme, continuing the company's application processor lineage with updated branding.
All C-series cores are currently 64-bit processors implementing the ARMv9.3-A architecture and feature integrated Scalable Matrix Extension 2 technology for accelerated AI workloads. The family emphasizes on-device artificial intelligence capabilities alongside traditional application processing performance.

C-series CPU variants

The C-series family currently includes four performance tiers: Nano, Pro, Premium and Ultra. Nano are in-order designs, the other three tiers provide out-of-order execution. Each tier targets different performance, energy and area efficiency requirements.

C1-series

The C1-series was introduced in September 2025 and is the first CPU family built on the Armv9.3 architecture. This architecture includes native support for SME2, providing hardware acceleration for matrix operations commonly used in AI and machine learning workloads.:
  • C1-Ultra is the flagship high-performance core, designed for demanding AI tasks and peak single-threaded performance. It features the widest micro-architecture in the industry and achieves significant performance improvements over previous-generation ARM cores through double-digit instructions per cycle gains. It succeeds Cortex-X925.
  • C1-Premium is described as ARM's first sub-flagship CPU, offering comparable performance to C1-Ultra in a significantly smaller area footprint. It maintains similar benchmark performance while reducing core size, making it suitable for designs where area efficiency is critical. It introduces a new tier.
  • C1-Pro is optimized for sustained performance across extended workloads such as gaming, video processing, and multitasking. It emphasizes performance per watt across the entire power range and includes enhanced branch prediction and memory system updates. It succeeds Cortex-A725.
  • C1-Nano is the smallest and most power-efficient core in the family, designed for always-on AI tasks, background processing, and low-power scenarios. It is particularly suited for wearables and compact consumer devices. It succeeds Cortex-A520.
SME2 is directly integrated into all C-series CPUs through the Armv9.3 architecture. This extension accelerates matrix-heavy operations used in large language models, media processing, speech recognition, computer vision, and multimodal applications.
The C1-DSU serves as the interconnect and shared cache infrastructure for C-series CPU clusters. It supports the latest architectural features and includes low-power optimizations, enabling improved bandwidth scaling and power efficiency compared to previous-generation DSU implementations.

Platform integration

The C-series CPUs are designed as part of the ARM Lumex compute subsystem platform, which provides a complete reference design for mobile and consumer devices. The platform approach allows chip manufacturers to integrate C-series cores with other ARM intellectual property and customize configurations to meet specific product requirements. Different combinations of C-series cores can be deployed across various device tiers.

Licensing

Like other ARM processor designs, C-series cores are not manufactured or sold directly by ARM Holdings. Instead, ARM licenses synthesizable hardware descriptions and development tools to semiconductor companies, which integrate the cores into custom system-on-chip designs. This licensing model allows manufacturers to optimize the implementation for specific process nodes, power targets, and feature sets.