Intel 8255


The Intel 8255 Programmable Peripheral Interface chip was developed and manufactured by Intel in the first half of the 1970s for the Intel 8080 microprocessor. The 8255 provides 24 parallel input/output lines with a variety of programmable operating modes.
The 8255 is a member of the MCS-85 family of chips, designed by Intel for use with their 8085 and 8086 microprocessors and their descendants. It was first available in a 40-pin DIP and later a 44-pin PLCC packages. It found wide applicability in digital processing systems and was later cloned by other manufacturers. The 82C55 is a CMOS version for higher speed and lower current consumption.
The functionality of the 8255 is now mostly embedded in larger VLSI processing chips as a sub-function. A CMOS version of the 8255 is still being made by Renesas but mostly used to expand the I/O of microcontrollers.

Similar chips

The 8255 has a similar function to the Motorola 6820 PIA from the Motorola 6800 family, also originally packaged as 40-pin DIL. The 8255 provides 24 I/O pins with four programmable direction bits: one for Port A, one for Port B, one for Port C and one for Port C. By contrast, the Motorola and MOS chips provide only 16 I/O pins plus 4 control pins, but the Motorola/MOS chips allow the direction of all I/O pins to be individually programmed. Both have configurations that will do a certain amount of automatic handshaking and interrupt generation.
Other comparable microprocessor I/O chips are the 2655 Programmable Peripheral Interface from the Signetics 2650 family, the Z80 PIO, the Western Design Center WDC 65C21, and the MOS Technology 6522 VIA and 6526 CIA which had considerable additional functionality such as timers and shift registers.

Variants

The industrial grade version of Intel ID8255A was available for US$17.55 in quantities of 100 and up. The available Intel 8255A-5 version was for USD $6.55 in quantities of 100 or more. The available 82C55A CMOS version was outsourced to Oki Electronic Industry Co., Ltd. The available package from Intel branded 82C55 in 44-pin PLCC of sampling at fourth quarter of 1985. In Eastern Europe, equivalent circuits were manufactured as the KR580VV55A in the Soviet Union and as the MHB8255A by Tesla in Czechoslovakia.

Applications

The 8255 was widely used in many microcomputer/microcontroller systems and home computers such as the SV-328 and all MSX models. The 8255 was used in the original IBM PC, PC/XT, PC/jr and clones, along with numerous homebuilt computers such as the N8VEM.

Function

The 8255 gives a CPU or digital system access to programmable parallel I/O.
The 8255 has 24 input/output pins. These are divided into three 8-bit ports. Port A and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output port or as two 4-bit input/output ports or to produce handshake signals for ports A and B.
The three ports are further grouped as follows:
  1. Group A consisting of port A and upper part of port C.
  2. Group B consisting of port B and lower part of port C.
Eight data lines are available to read/write data into the ports or control register under the status of the RD and WR, which are active-low signals for read and write operations respectively. Address lines A1 and A0 allow to access a data register for each port or a control register, as listed below:
The control signal chip select CS is used to enable the 8255 chip. It is an active-low signal, i.e., when CS = 0, the 8255 is enabled. The RESET input is connected to the RESET line of system like 8085, 8086, etc., so that when the system is reset, all the ports are initialized as input lines. This is done to prevent 8255 and/or any peripheral connected to it from being destroyed due to mismatch of port direction settings. As an example, consider an input device connected to 8255 at port A. If from the previous operation, port A is initialized as an output port and if 8255 is not reset before using the current configuration, then there is a possibility of damage of either the input device connected or 8255 or both, since both 8255 and the device connected will be sending out data.
The control register is an 8-bit register used to select the modes of operation and input/output designation of the ports.

Operational modes of 8255

There are two basic operational modes of 8255:
  • Bit Set/Reset mode.
  • Input/Output mode.
The two modes are selected on the basis of the value present at the D7 bit of the control word register. When D7 = 1, 8255 operates in I/O mode, and when D7 = 0, it operates in the BSR mode.

Bit Set/Reset (BSR) mode

The Bit Set/Reset mode is available on port C only. Each line of port C can be set or reset by writing a suitable value to the control word register. BSR mode and I/O mode are independent and selection of BSR mode does not affect the operation of other ports in I/O mode.
  • D7 bit is always 0 for BSR mode.
  • Bits D6, D5 and D4 are don't care bits.
  • Bits D3, D2 and D1 are used to select the pin of Port C.
  • Bit D0 is used to set/reset the selected pin of Port C.
Selection of port C pin is determined as follows:
D3D2D1Bit/pin of port C selected
000PC0
001PC1
010PC2
011PC3
100PC4
101PC5
110PC6
111PC7

As an example, if it is needed that PC5 be set, then in the control word,
  1. Since it is BSR mode, D7 = '0'.
  2. Since D4, D5, D6 are not used, assume them to be '0'.
  3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
  4. PC5 has to be set, hence, D0 = '1'.
Thus, as per the above values, 0B will be loaded into the Control Word Register.
D7D6D5D4D3D2D1D0
00001011

Input/Output mode

This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O modes:
  1. Mode 0 - Simple I/O
  2. Mode 1 - Strobed I/O
  3. Mode 2 - Strobed Bi-directional I/O

    Control Word format

  • D0, D1, D3, D4 are assigned for port C lower, port B, port C upper and port A respectively. When these bits are 1, the corresponding port acts as an input port. For e.g., if D0 = D4 = 1, then lower port C and port A act as input ports. If these bits are 0, then the corresponding port acts as an output port. For e.g., if D1 = D3 = 0, then port B and upper port C act as output ports.
  • D2 is used for mode selection of Group B. When D2 = 0, mode 0 is selected and when D2 = 1, mode 1 is selected.
  • D5 & D6 are used for mode selection of Group A. The selection is done as follows:
D6D5Mode
000
011
1X2

  • As it is I/O mode, D7 = 1.
For example, if port B and upper port C have to be initialized as input ports and lower port C and port A as output ports :
  1. Since it is an I/O mode, D7 = 1.
  2. Mode selection bits, D2, D5, D6 are all 0 for mode 0 operation.
  3. Port B and upper port C should operate as Input ports, hence, D1 = D3 = 1.
  4. Port A and lower port C should operate as Output ports, hence, D4 = D0 = 0.
Hence, for the desired operation, the control word register will have to be loaded with "10001010" = 8A .

Mode 0 - simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A, port B provide simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port.
The input/output features in mode 0 are as follows:
  1. Output ports are latched.
  2. Input ports are buffered, not latched.
  3. Ports do not have handshake or interrupt capability.
  4. With 4 ports, 16 different combinations of I/O are possible.
'Latched' means the bits are put into a storage register which holds its output constant even if the inputs change after being latched.
The 8255's outputs are latched to hold the last data written to them. This is required because the data only stays on the bus for one cycle. So, without latching, the outputs would become invalid as soon as the write cycle finishes.
The inputs are not latched because the CPU only has to read their current values, then store the data in a CPU register or memory if it needs to be referenced at a later time. If an input changes while the port is being read then the result may be indeterminate.

Mode 0 – input mode

  • In the input mode, the 8255 gets data from the external peripheral ports and the CPU reads the received data via its data bus.
  • The CPU first selects the 8255 chip by making CS low. Then it selects the desired port using A0 and A1 lines.
  • The CPU then issues an RD signal to read the data from the external peripheral device via the system data bus.