List of 7400-series integrated circuits
The following is a list of 7400-series digital logic integrated circuits. In the mid-1960s, the original 7400-series integrated circuits were introduced by Texas Instruments with the prefix "SN" to create the name SN74xx. Due to the popularity of these parts, other manufacturers released pin-to-pin compatible logic devices and kept the 7400 sequence number as an aid to identification of compatible parts. However, other manufacturers use different prefixes and suffixes on their part numbers.
Overview
Some TTL logic parts were made with an extended military-specification temperature range. These parts are prefixed with 54 instead of 74 in the part number.A short-lived 64 prefix on Texas Instruments parts indicated an industrial temperature range; this prefix had been dropped from the TI literature by 1973. Most recent 7400-series parts are fabricated in CMOS or BiCMOS technology rather than TTL. Surface-mount parts with a single gate are prefixed with 741G instead of 74.
Some manufacturers released some 4000-series equivalent CMOS circuits with a 74 prefix, for example, the 74HC4066 was a replacement for the 4066 with slightly different electrical characteristics. See List of 4000-series integrated circuits.
Conversely, the 4000-series has "borrowed" from the 7400 series such as the CD40193 and CD40161 being pin-for-pin functional replacements for 74C193 and 74C161.
Older TTL parts made by manufacturers such as Signetics, Motorola, Mullard and Siemens may have different numeric prefix and numbering series entirely, such as in the European FJ family FJH101 is an 8-input NAND gate like a 7430.
A few alphabetic characters to designate a specific logic subfamily may immediately follow the 74 or 54 in the part number, e.g., 74LS74 for low-power Schottky. Some CMOS parts such as 74HCT74 for high-speed CMOS with TTL-compatible input thresholds are functionally similar to the TTL part. Not all functions are available in all families.
The generic descriptive feature of these alphabetic characters was diluted by various companies participating in the market at its peak and are not always consistent especially with more recent offerings. The National Semiconductor trademarks of the words FAST and FACT are usually cited in the descriptions from other companies when describing their own unique designations.
In a few instances, such as the 7478 and 74107, the same suffix in different families do not have completely equivalent logic functions.
Another extension to the series is the 7416xxx variant, representing mostly the 16-bit-wide counterpart of otherwise 8-bit-wide "base" chips with the same three ending digits. Thus e.g. a "7416373" would be the 16-bit-wide equivalent of a "74373". Some 7416xxx parts, however, do not have a direct counterpart from the standard 74xxx range but deliver new functionality instead, which needs making use of the 7416xxx series' higher pin count. For more details, refer primarily to the Texas Instruments documentation mentioned in the [|References] section.
For CMOS subfamilies, read "open drain" for "open collector" in the table below.
There are a few numeric suffixes that have multiple conflicting assignments, such as the 74453.
Logic gates
Since there are numerous 7400-series parts, the following groups related parts to make it easier to pick a useful part number. This section only includes combinational logic gates.For part numbers in this section, "x" is the 7400-series logic family, such as LS, ALS, HCT, AHCT, HC, AHC, LVC,...
;Normal inputs / push–pull outputs
;Schmitt-trigger inputs / push–pull outputs
;Normal inputs / open-collector outputs
;Schmitt-trigger inputs / three-state outputs
;AND-OR-invert logic gates
- SN5450 = dual 2-2 AOI gate, one is expandable
- SN74LS51 = 2-2 AOI gate and 3-3 AOI gate
- SN54LS54 = single 2-3-3-2 AOI gate
Larger footprints
For the following table:
- Part number column the "x" is a place holder for the logic subfamily name. For example, 74x00 in "LS" logic family would be "74LS00".
- Description column simplified to make it easier to sort, thus isn't identical to datasheet title. The terms Schmitt trigger, open-collector/open-drain, three-state were moved to the input and output columns to make it easier to sort by those features.
- Input column a blank cell means a normal input for the logic family type.
- Output column a blank cell means a "totem pole" output, also known as a push–pull output, with the ability to drive ten standard inputs of the same logic subfamily. Outputs with higher output currents are often called drivers or buffers.
- Pins column number of pins for the dual in-line package version; a number in parentheses indicates that there is no known dual in-line package version of this IC.
| Units | Description | Input | Output | Pins | Datasheet | |
| 74x00 | 4 | quad 2-input NAND gate | 14 | |||
| 74x01 | 4 | quad 2-input NAND gate; different pinout for 74H01 | open-collector | 14 | ||
| 74x02 | 4 | quad 2-input NOR gate | 14 | |||
| 74x03 | 4 | quad 2-input NAND gate | open-collector | 14 | ||
| 74x04 | 6 | hex inverter gate | 14 | |||
| 74x05 | 6 | hex inverter gate | open-collector | 14 | ||
| 74x06 | 6 | hex inverter gate | open-collector 30 V / 40 mA | 14 | ||
| 74x07 | 6 | hex buffer gate | open-collector 30 V / 40 mA | 14 | ||
| 74x08 | 4 | quad 2-input AND gate | 14 | |||
| 74x09 | 4 | quad 2-input AND gate | open-collector | 14 | ||
| 74x10 | 3 | triple 3-input NAND gate | 14 | |||
| 74x11 | 3 | triple 3-input AND gate | 14 | |||
| 74x12 | 3 | triple 3-input NAND gate | open-collector | 14 | ||
| 74x13 | 2 | dual 4-input NAND gate | Schmitt trigger | 14 | ||
| 74x14 | 6 | hex inverter gate | Schmitt trigger | 14 | ||
| 74x15 | 3 | triple 3-input AND gate | open-collector | 14 | ||
| 74x16 | 6 | hex inverter gate | open-collector 15 V / 40 mA | 14 | ||
| 74x17 | 6 | hex buffer gate | open-collector 15 V / 40 mA | 14 | ||
| 74x18 | 2 | dual 4-input NAND gate | Schmitt trigger | 14 | ||
| 74x19 | 6 | hex inverter gate | Schmitt trigger | 14 | ||
| 74x20 | 2 | dual 4-input NAND gate | 14 | |||
| 74x21 | 2 | dual 4-input AND gate | 14 | |||
| 74x22 | 2 | dual 4-input NAND gate | open-collector | 14 | ||
| 74x23 | 2 | dual 4-input NOR gate with strobe, one gate expandable with 74x60 | 16 | |||
| 74x24 | 4 | quad 2-input NAND gate | Schmitt trigger | 14 | ||
| 74x25 | 2 | dual 4-input NOR gate with strobe | 14 | |||
| 74x26 | 4 | quad 2-input NAND gate | open-collector 15 V | 14 | ||
| 74x27 | 3 | triple 3-input NOR gate | 14 | |||
| 74x28 | 4 | quad 2-input NOR gate | driver NO=30 | 14 | ||
| 74x29 | 2 | dual 4-input NOR gate | 14 | |||
| 74x30 | 1 | single 8-input NAND gate | 14 | |||
| 74x31 | 6 | hex delay elements | 16 | |||
| 74x32 | 4 | quad 2-input OR gate | 14 | |||
| 74x33 | 4 | quad 2-input NOR gate | open-collector driver NO=30 | 14 | ||
| 74x34 | 6 | hex buffer gate | 14 | |||
| 74x35 | 6 | hex buffer gate | open-collector | 14 | ||
| 74x36 | 4 | quad 2-input NOR gate | 14 | |||
| 74x37 | 4 | quad 2-input NAND gate | driver NO=30 | 14 | ||
| 74x38 | 4 | quad 2-input NAND gate | open-collector driver NO=30 | 14 | ||
| 74x39 | 4 | quad 2-input NAND gate | open-collector 60 mA | 14 | ||
| 74x40 | 2 | dual 4-input NAND gate | driver NO=30 | 14 | ||
| 74x41 | 1 | BCD to decimal decoder / Nixie tube driver | open-collector 70 V | 16 | ||
| 74x42 | 1 | BCD to decimal decoder | 16 | |||
| 74x43 | 1 | excess-3 to decimal decoder | 16 | |||
| 74x44 | 1 | Gray code to decimal decoder | 16 | |||
| 74x45 | 1 | BCD to decimal decoder/driver | open-collector 30 V / 80 mA | 16 | ||
| 74x46 | 1 | BCD to 7-segment display decoder/driver | open-collector 30 V | 16 | ||
| 74x47 | 1 | BCD to 7-segment decoder/driver | open-collector 15 V | 16 | ||
| 74x48 | 1 | BCD to 7-segment decoder/driver | open-collector, 2 kΩ pull-up | 16 | ||
| 74x49 | 1 | BCD to 7-segment decoder/driver | open-collector | 14 | ||
| 74x50 | 2 | dual 2-2-input AND-OR-Invert gate, one gate expandable | 14 | |||
| 7451, 74H51, 74S51 | 2 | dual 2-2-input AND-OR-Invert gate | 14 | |||
| 74L51, 74LS51 | 2 | 3-3-input AND-OR-Invert gate and 2-2-input AND-OR-Invert gate | 14 | |||
| 74x52 | 1 | 3-2-2-2-input AND-OR gate, expandable with 74x61 | 14 | |||
| 7453 | 1 | 2-2-2-2-input AND-OR-Invert gate, expandable | 14 | |||
| 74H53 | 1 | 3-2-2-2-input AND-OR-Invert gate, expandable | 14 | |||
| 7454 | 1 | 2-2-2-2-input AND-OR-Invert gate | 14 | |||
| 74H54 | 1 | 3-2-2-2-input AND-OR-Invert gate | 14 | |||
| 74L54, 74LS54 | 1 | 3-3-2-2-input AND-OR-Invert gate | 14 | |||
| 74x55 | 1 | 4-4-input AND-OR-Invert gate, 74H55 is expandable | 14 | |||
| 74x56 | 1 | 50:1 frequency divider | 8 | |||
| 74x57 | 1 | 60:1 frequency divider | 8 | |||
| 74x58 | 2 | 3-3-input AND-OR gate and 2-2-input AND-OR gate | 14 | |||
| 74x59 | 2 | dual 3-2-input AND-OR-Invert gate | 14 | |||
| 74x60 | 2 | dual 4-input expander for 74x23, 74x50, 74x53, 74x55 | 14 | |||
| 74x61 | 3 | triple 3-input expander for 74x52 | 14 | |||
| 74x62 | 1 | 3-3-2-2-input AND-OR expander for 74x50, 74x53, 74x55 | 14 | |||
| 74x63 | 6 | hex current sensing interface gates | 14 | |||
| 74x64 | 1 | 4-3-2-2-input AND-OR-Invert gate | 14 | |||
| 74x65 | 1 | 4-3-2-2 input AND-OR-Invert gate | open-collector | 14 | ||
| 74x67 | 1 | AND gated J-K master-slave flip-flop, asynchronous preset and clear | ||||
| 74L68 | 2 | dual J-K flip-flop, asynchronous clear | ||||
| 74LS68 | 2 | dual 4-bit decade counters | 16 | |||
| 74L69 | 2 | dual J-K flip-flop, asynchronous preset, shared clock and clear | ||||
| 74LS69 | 2 | dual 4-bit binary counters | 16 | |||
| 74x70 | 1 | AND-gated positive edge triggered J-K flip-flop, asynchronous preset and clear | 14 | |||
| 74H71 | 1 | AND-OR-gated J-K master-slave flip-flop, preset | 14 | |||
| 74L71 | 1 | AND-gated R-S master-slave flip-flop, preset and clear | 14 | |||
| 74x72 | 1 | AND gated J-K master-slave flip-flop, asynchronous preset and clear | 14 | |||
| 74x73 | 2 | dual J-K flip-flop, asynchronous clear | 14 | |||
| 74x74 | 2 | dual D positive edge triggered flip-flop, asynchronous clear & preset, Q & /Q outputs | 14 | |||
| 74x75 | 1 | 4-bit bistable latch, complementary outputs | 16 | |||
| 74x76 | 2 | dual J-K flip-flop, asynchronous preset and clear | 16 | |||
| 74x77 | 1 | 4-bit bistable latch | 14 | |||
| 74H78 | 2 | dual positive pulse triggered J-K flip-flop, preset, shared clock and clear | 14 | |||
| 74L78 | 2 | dual positive pulse triggered J-K flip-flop, preset, shared clock and clear | 14 | |||
| 74LS78 | 2 | dual negative edge triggered J-K flip-flop, preset, shared clock and clear | 14 | |||
| 74x79 | 2 | dual D positive edge triggered flip-flop, asynchronous preset and clear | 14 | |||
| 74x80 | 1 | gated full adder | 14 | |||
| 74x81 | 1 | 16-bit RAM | 14 | |||
| 74x82 | 1 | 2-bit binary full adder | 14 | |||
| 74x83 | 1 | 4-bit binary full adder | 16 | |||
| 74x84 | 1 | 16-bit RAM | 16 | |||
| 74x85 | 1 | 4-bit magnitude comparator | 16 | |||
| 74x86 | 4 | quad 2-input XOR gate | 14 | |||
| 74x87 | 1 | 4-bit true/complement/zero/one element | 14 | |||
| 74x88 | 1 | 256-bit ROM | open-collector | 16 | ||
| 74x89 | 1 | 64-bit RAM, 4 data inputs, 4 inverted data outputs | open-collector | 16 | ||
| 74x90 | 1 | decade counter | 14 | |||
| 74x91 | 1 | 8-bit shift register, serial in, serial out, gated input | 14 | |||
| 74x92 | 1 | divide-by-12 counter | 14 | |||
| 74x93 | 1 | 4-bit binary counter ; different pinout for 74L93 | 14 | |||
| 74x94 | 1 | 4-bit shift register, dual asynchronous presets | 16 | |||
| 74x95 | 1 | 4-bit shift register, parallel in, parallel out, serial input; different pinout for 74L95 | 14 | |||
| 74x96 | 1 | 5-bit parallel-in/parallel-out shift register, asynchronous preset | 16 | |||
| 74x97 | 1 | synchronous 6-bit binary rate multiplier | 16 | |||
| 74x98 | 1 | 4-bit data selector/storage register | 16 | |||
| 74x99 | 1 | 4-bit bidirectional universal shift register | 16 | |||
| Units | Description | Input | Output | Pins | Datasheet | |
| 74x100 | 2 | dual 4-bit bistable latch | 24 | |||
| 74x101 | 1 | AND-OR-gated J-K negative-edge-triggered flip-flop, preset | 14 | |||
| 74x102 | 1 | AND-gated J-K negative-edge-triggered flip-flop, preset and clear | 14 | |||
| 74x103 | 2 | dual J-K negative-edge-triggered flip-flop, clear | 14 | |||
| 74x104 | 1 | J-K master-slave flip-flop | 14 | |||
| 74x105 | 1 | J-K master-slave flip-flop, J2 and K2 inverted | 14 | |||
| 74x106 | 2 | dual J-K negative-edge-triggered flip-flop, preset and clear | 16 | |||
| 74x107 | 2 | dual J-K flip-flop, clear | 14 | |||
| 74x108 | 2 | dual J-K negative-edge-triggered flip-flop, preset, shared clock and clear | 14 | |||
| 74x109 | 2 | dual J-NotK positive-edge-triggered flip-flop, clear and preset | 16 | |||
| 74x110 | 1 | AND-gated J-K master-slave flip-flop, data lockout | 14 | |||
| 74x111 | 2 | dual J-K master-slave flip-flop, data lockout, reset, set | 16 | |||
| 74x112 | 2 | dual J-K negative-edge-triggered flip-flop, clear & preset, Q & /Q outputs | 16 | |||
| 74x113 | 2 | dual J-K negative-edge-triggered flip-flop, preset | 14 | |||
| 74x114 | 2 | dual J-K negative-edge-triggered flip-flop, preset, shared clock and clear | 14 | |||
| 74x115 | 2 | dual J-K master-slave flip-flop, data lockout, reset | 14 | |||
| 74116, 74L116 | 2 | dual 4-bit latch, clear | 24 | |||
| 74H116 | 1 | AND-gated J-K flip flop | 14 | |||
| 74x117 | 1 | AND-gated J-K flip flop, one J and K input inverted | 14 | |||
| 74x118 | 6 | hex set/reset latch, shared reset | 16 | |||
| 74119 | 6 | hex set/reset latch | 24 | |||
| 74H119 | 2 | dual J-K flip-flop, shared clock and clear | 14 | |||
| 74120 | 2 | dual pulse synchronizer/drivers | 15 kΩ pull-up | 16 | ||
| 74H120 | 2 | dual J-K flip-flop, separate clock inputs | 14 | |||
| 74x121 | 1 | monostable multivibrator | Schmitt trigger | 14 | ||
| 74x122 | 1 | retriggerable monostable multivibrator, clear | 14 | |||
| 74x123 | 2 | dual retriggerable monostable multivibrator, clear | 16 | |||
| 74x124 | 2 | dual voltage-controlled oscillator | analog | 16 | ||
| 74x125 | 4 | quad bus buffer, negative enable | three-state | 14 | ||
| 74x126 | 4 | quad bus buffer, positive enable | three-state | 14 | ||
| 74x128 | 4 | quad 2-input NOR gate | driver 50 Ω | 14 | ||
| 74x130 | 2 | retriggerable monostable multivibrator | 16 | |||
| 74131 | 4 | quad 2-input AND gate | open-collector 15 V | 14 | ||
| 74AS131, 74ALS131 | 1 | 3-to-8 line decoder/demultiplexer, address register, inverting outputs | 16 | |||
| 74x132 | 4 | quad 2-input NAND gate | Schmitt trigger | 14 | ||
| 74x133 | 1 | single 13-input NAND gate | 16 | |||
| 74x134 | 1 | single 12-input NAND gate | three-state | 16 | ||
| 74x135 | 4 | quad XOR/XNOR gate, two inputs to select logic type | 16 | |||
| 74x136 | 4 | quad 2-input XOR gate | open-collector | 14 | ||
| 74x137 | 1 | 3-to-8 line decoder/demultiplexer, address latch, inverting outputs | 16 | |||
| 74x138 | 1 | 3-to-8 line decoder/demultiplexer, inverting outputs | 16 | |||
| 74x139 | 2 | dual 2-to-4 line decoder/demultiplexer, inverting outputs | 16 | |||
| 74x140 | 2 | dual 4-input NAND gate | driver 50 Ω | 14 | ||
| 74x141 | 1 | BCD to decimal decoder/driver for cold-cathode indicator / Nixie tube | open-collector 60 V | 16 | ||
| 74x142 | 1 | decade counter/latch/decoder/driver for Nixie tubes | open-collector 60 V | 16 | ||
| 74x143 | 1 | decade counter/latch/decoder/7-segment driver | constant current 15 mA | 24 | ||
| 74x144 | 1 | decade counter/latch/decoder/7-segment driver | open-collector 15 V / 25 mA | 24 | ||
| 74x145 | 1 | BCD to decimal decoder/driver | open-collector 15 V / 80 mA | 16 | ||
| 74x146 | 1 | 3-to-8 line decoder | ||||
| 74x147 | 1 | 10-line to 4-line priority encoder | 16 | |||
| 74x148 | 1 | 8-line to 3-line priority encoder | 16 | |||
| 74x149 | 1 | 8-line to 8-line priority encoder | 20 | |||
| 74x150 | 1 | 16-line to 1-line data selector/multiplexer | 24 | |||
| 74x151 | 1 | 8-line to 1-line data selector/multiplexer | 16 | |||
| 74x152 | 1 | 8-line to 1-line data selector/multiplexer, inverting output | 14 | |||
| 74x153 | 2 | dual 4-line to 1-line data selector/multiplexer, non-inverting outputs | 16 | |||
| 74x154 | 1 | 4-to-16 line decoder/demultiplexer, inverting outputs | 24 | |||
| 74x155 | 2 | dual 2-to-4 line decoder/demultiplexer, inverting outputs | 16 | |||
| 74x156 | 2 | dual 2-to-4 line decoder/demultiplexer, inverting outputs | open-collector | 16 | ||
| 74x157 | 4 | quad 2-line to 1-line data selector/multiplexer, non-inverting outputs | 16 | |||
| 74x158 | 4 | quad 2-line to 1-line data selector/multiplexer, inverting outputs | 16 | |||
| 74x159 | 1 | 4-to-16 line decoder/demultiplexer | open-collector | 24 | ||
| 74x160 | 1 | synchronous presettable 4-bit decade counter, asynchronous clear | 16 | |||
| 74x161 | 1 | synchronous presettable 4-bit binary counter, asynchronous clear | 16 | |||
| 74x162 | 1 | synchronous presettable 4-bit decade counter, synchronous clear | 16 | |||
| 74x163 | 1 | synchronous presettable 4-bit binary counter, synchronous clear | 16 | |||
| 74x164 | 1 | 8-bit serial-in parallel-out shift register, asynchronous clear, not output latch | 14 | |||
| 74x165 | 1 | 8-bit parallel-in serial-out shift register, parallel load, complementary outputs | 16 | |||
| 74x166 | 1 | parallel-load 8-bit shift register | 16 | |||
| 74x167 | 1 | synchronous decade rate multiplier | 16 | |||
| 74x168 | 1 | synchronous presettable 4-bit up/down decade counter | 16 | |||
| 74x169 | 1 | synchronous presettable 4-bit up/down binary counter | 16 | |||
| 74x170 | 1 | 16-bit register file | open-collector | 16 | ||
| 74x171 | 4 | quad D flip-flops, shared clock and clear | 16 | |||
| 74x172 | 1 | 16-bit multiple port register file | three-state | 24 | ||
| 74x173 | 4 | quad D flip-flop, shared clock and asynchronous clear and enable, Q & /Q outputs | three-state | 16 | ||
| 74x174 | 6 | hex D flip-flop, shared clock and asynchronous clear, Q outputs | 16 | |||
| 74x175 | 4 | quad D edge-triggered flip-flop, shared clock and asynchronous clear, Q & /Q outputs | 16 | |||
| 74x176 | 1 | presettable decade counter/latch | 14 | |||
| 74x177 | 1 | presettable binary counter/latch | 14 | |||
| 74x178 | 1 | 4-bit parallel-access shift register | 14 | |||
| 74x179 | 1 | 4-bit parallel-access shift register, asynchronous clear input, complementary Qd output | 16 | |||
| 74x180 | 1 | 9-bit odd/even parity bit generator and checker | 14 | |||
| 74x181 | 1 | 4-bit arithmetic logic unit and function generator | 24 | |||
| 74x182 | 1 | lookahead carry generator | 16 | |||
| 74x183 | 2 | dual carry-save full adder | 14 | |||
| 74x184 | 1 | BCD to binary converter | open-collector | 16 | ||
| 74x185 | 1 | 6-bit binary to BCD converter | open-collector | 16 | ||
| 74x186 | 1 | 512-bit ROM | open-collector | 24 | ||
| 74x187 | 1 | 1024-bit ROM | open-collector | 16 | ||
| 74x188 | 1 | 256-bit PROM | open-collector | 16 | ||
| 74x189 | 1 | 64-bit RAM, 4 data inputs, 4 inverted data outputs | three-state | 16 | ||
| 74x190 | 1 | synchronous presettable up/down 4-bit decade counter | 16 | |||
| 74x191 | 1 | synchronous presettable up/down 4-bit binary counter | 16 | |||
| 74x192 | 1 | synchronous presettable up/down 4-bit decade counter, clear | 16 | |||
| 74x193 | 1 | synchronous presettable up/down 4-bit binary counter, clear | 16 | |||
| 74x194 | 1 | 4-bit bidirectional universal shift register | 16 | |||
| 74x195 | 1 | 4-bit parallel-access shift register | 16 | |||
| 74x196 | 1 | presettable 4-bit decade counter/latch | 14 | |||
| 74x197 | 1 | presettable 4-bit binary counter/latch | 14 | |||
| 74x198 | 1 | 8-bit bidirectional universal shift register | 24 | |||
| 74x199 | 1 | 8-bit universal shift register, J-NotK serial inputs | 24 | |||
| Units | Description | Input | Output | Pins | Datasheet | |
| 74x200 | 1 | 256-bit RAM | three-state | 16 | ||
| 74x201 | 1 | 256-bit RAM | three-state | 16 | ||
| 74x202 | 1 | 256-bit RAM with power down | three-state | 16 | ||
| 74x206 | 1 | 256-bit RAM | open-collector | 16 | ||
| 74x207 | 1 | 1024-bit RAM | three-state | 16 | ||
| 74x208 | 1 | 1024-bit RAM, separate data in- and outputs | three-state | 20 | ||
| 74x209 | 1 | 1024-bit RAM | three-state | 16 | ||
| 74x210 | 8 | octal buffer, inverting | three-state | 20 | ||
| 74x211 | 1 | 144-bit RAM with output latch | three-state | 20 | ||
| 74x212 | 1 | 144-bit RAM | three-state | 20 | ||
| 74x213 | 1 | 192-bit RAM | three-state | 20 | ||
| 74x214 | 1 | 1024-bit RAM | three-state | 16 | ||
| 74x215 | 1 | 1024-bit RAM with power-down mode | three-state | 16 | ||
| 74x216 | 1 | 256-bit RAM, common I/O | three-state | 16 | ||
| 74x217 | 1 | 256-bit RAM | three-state | 20 | ||
| 74x218 | 1 | 256-bit RAM | three-state | 20 | ||
| 74x219 | 1 | 64-bit RAM, non-inverting outputs | three-state | 16 | ||
| 74x221 | 2 | dual monostable multivibrator | Schmitt trigger | 16 | ||
| 74x222 | 1 | 64-bit FIFO memory, synchronous, input/output ready enable | three-state | 20 | ||
| 74x224 | 1 | 64-bit FIFO memory, synchronous | three-state | 16 | ||
| 74x225 | 1 | 80-bit FIFO memory, asynchronous | three-state | 20 | ||
| 74x226 | 1 | 4-bit parallel latched bus transceiver | three-state | 16 | ||
| 74x227 | 1 | 64-bit FIFO memory, synchronous, input/output ready enable | open-collector | 20 | ||
| 74x228 | 1 | 64-bit FIFO memory, synchronous | open-collector | 20 | ||
| 74x229 | 1 | 80-bit FIFO memory, asynchronous | three-state | 20 | ||
| 74x230 | 2 | dual 4-bit buffer/driver, one inverted, one non-inverted; negative enable | three-state | 20 | ||
| 74x231 | 2 | dual 4-bit buffer/driver, both inverted; one positive and one negative enable | three-state | 20 | ||
| 74x232 | 1 | 64-bit FIFO memory, asynchronous | three-state | 16 | ||
| 74x233 | 1 | 80-bit FIFO memory, asynchronous | three-state | 20 | ||
| 74x234 | 1 | 256-bit FIFO memory, asynchronous | three-state | 16 | ||
| 74x235 | 1 | 320-bit FIFO memory, asynchronous | three-state | 20 | ||
| 74x236 | 1 | 256-bit FIFO memory, asynchronous | three-state | 16 | ||
| 74x237 | 1 | 3-to-8 line decoder/demultiplexer, address latch, active high outputs | 16 | |||
| 74x238 | 1 | 3-to-8 line decoder/demultiplexer, active high outputs | 16 | |||
| 74x239 | 2 | dual 2-to-4 line decoder/demultiplexer, active high outputs | 16 | |||
| 74x240 | 8 | octal buffer, inverting outputs | Schmitt trigger | three-state | 20 | |
| 74x241 | 8 | octal buffer, non-inverting outputs | Schmitt trigger | three-state | 20 | |
| 74x242 | 4 | quad bus transceiver, inverting outputs | Schmitt trigger | three-state | 14 | |
| 74x243 | 4 | quad bus transceiver, non-inverting outputs | Schmitt trigger | three-state | 14 | |
| 74x244 | 8 | octal buffer, non-inverting outputs | Schmitt trigger | three-state | 20 | |
| 74x245 | 8 | octal bus transceiver, non-inverting outputs | Schmitt trigger | three-state | 20 | |
| 74x246 | 1 | BCD to 7-segment decoder/driver | open-collector 30 V | 16 | ||
| 74x247 | 1 | BCD to 7-segment decoder/driver | open-collector 15 V | 16 | ||
| 74x248 | 1 | BCD to 7-segment decoder/driver | open-collector, 2 kΩ pull-up | 16 | ||
| 74x249 | 1 | BCD to 7-segment decoder/driver | open-collector | 16 | ||
| 74x250 | 1 | 1 of 16 data selector/multiplexer | three-state | 24 | ||
| 74x251 | 1 | 8-line to 1-line data selector/multiplexer, complementary outputs | three-state | 16 | ||
| 74x253 | 2 | dual 4-line to 1-line data selector/multiplexer | three-state | 16 | ||
| 74x255 | 2 | dual 2-to-4 line decoder/demultiplexer, inverting outputs | three-state | 16 | ||
| 74x256 | 2 | dual 4-bit addressable latch | 16 | |||
| 74x257 | 4 | quad 2-line to 1-line data selector/multiplexer, non-inverting outputs | three-state | 16 | ||
| 74x258 | 4 | quad 2-line to 1-line data selector/multiplexer, inverting outputs | three-state | 16 | ||
| 74x259 | 1 | 8-bit bit addressable input latch with clr | 16 | |||
| 74x260 | 2 | dual 5-input NOR gate | 14 | |||
| 74x261 | 1 | 2-bit by 4-bit parallel binary multiplier | 16 | |||
| 74x262 | 1 | 5760-bit ROM | three-state | 20 | ||
| 74x264 | 1 | look ahead carry generator | 16 | |||
| 74x265 | 4 | quad complementary output elements | 16 | |||
| 74x266 | 4 | quad 2-input XNOR gate | open-collector | 14 | ||
| 74x268 | 6 | hex D-type latches, shared enable and output control | three-state | 16 | ||
| 74x269 | 1 | 8-bit bidirectional binary counter | 24 | |||
| 74x270 | 1 | 2048-bit ROM | open-collector | 16 | ||
| 74x271 | 1 | 2048-bit ROM | open-collector | 20 | ||
| 74x273 | 1 | 8-bit register, asynchronous clear | 20 | |||
| 74x274 | 1 | 4-bit by 4-bit binary multiplier | three-state | 20 | ||
| 74x275 | 1 | 7-bit slice Wallace tree | three-state | 16 | ||
| 74x276 | 4 | quad J-NotK edge-triggered flip-flops, separate clocks, shared preset and clear | 20 | |||
| 74x278 | 1 | 4-bit cascadeable priority registers, latched data inputs | 14 | |||
| 74x279 | 4 | quad set-reset latch | 16 | |||
| 74x280 | 1 | 9-bit odd/even parity bit generator/checker | 14 | |||
| 74x281 | 1 | 4-bit parallel binary accumulator | 24 | |||
| 74x282 | 1 | look-ahead carry generator, selectable carry inputs | 20 | |||
| 74x283 | 1 | 4-bit binary full adder | 16 | |||
| 74x284 | 1 | 4-bit by 4-bit parallel binary multiplier | 16 | |||
| 74x285 | 1 | 4-bit by 4-bit parallel binary multiplier | 16 | |||
| 74x286 | 1 | 9-bit parity generator/checker, bus driver parity I/O port | 14 | |||
| 74x287 | 1 | 1024-bit PROM | three-state | 16 | ||
| 74x288 | 1 | 256-bit PROM | three-state | 16 | ||
| 74x289 | 1 | 64-bit RAM, 4 data inputs, 4 inverted data outputs | open-collector | 16 | ||
| 74x290 | 1 | decade counter | 14 | |||
| 74x292 | 1 | programmable frequency divider/digital timer | 16 | |||
| 74x293 | 1 | 4-bit binary counter | 14 | |||
| 74x294 | 1 | programmable frequency divider/digital timer | 16 | |||
| 74x295 | 1 | 4-bit bidirectional shift register | three-state | 14 | ||
| 74x297 | 1 | digital phase-locked loop filter | 16 | |||
| 74x298 | 4 | quad 2-input multiplexer, storage | 16 | |||
| 74x299 | 1 | 8-bit bidirectional universal shift/storage register | three-state | 20 | ||
| Units | Description | Input | Output | Pins | Datasheet | |
| 74x300 | 1 | 256-bit RAM | open-collector | 16 | ||
| 74x301 | 1 | 256-bit RAM | open-collector | 16 | ||
| 74x302 | 1 | 256-bit RAM | open-collector | 16 | ||
| 74x303 | 1 | octal divide-by-2 clock driver, 2 outputs inverted | 16 | |||
| 74x304 | 1 | octal divide-by-2 clock driver | 16 | |||
| 74x305 | 1 | octal divide-by-2 clock driver, 4 outputs inverted | 16 | |||
| 74x306 | 1 | 8-bit LV-TTL to GTL+ bus transceiver | three-state and open-collector | |||
| 74x309 | 1 | 1024-bit RAM | open-collector | 16 | ||
| 74x310 | 8 | octal buffer, inverting | Schmitt trigger | three-state | 20 | |
| 74x311 | 1 | 144-bit RAM with output latch | open-collector | 20 | ||
| 74x312 | 1 | 144-bit RAM | open-collector | 20 | ||
| 74x313 | 1 | 192-bit RAM | open-collector | 20 | ||
| 74x314 | 1 | 1024-bit RAM | open-collector | 16 | ||
| 74x315 | 1 | 1024-bit RAM with power-down mode | open-collector | 16 | ||
| 74x316 | 1 | 256-bit RAM, common I/O | open-collector | 16 | ||
| 74x317 | 1 | 256-bit RAM | open-collector | 20 | ||
| 74x318 | 1 | 256-bit RAM | open-collector | 20 | ||
| 74x319 | 1 | 64-bit RAM | open-collector | 16 | ||
| 74x320 | 1 | crystal-controlled oscillator | 16 | |||
| 74x321 | 1 | crystal-controlled oscillators, F/2 and F/4 count-down outputs | 16 | |||
| 74x322 | 1 | 8-bit shift register, sign extend | three-state | 20 | ||
| 74x323 | 1 | 8-bit bidirectional universal shift/storage register, synchronous clear | three-state | 20 | ||
| 74x324 | 1 | voltage-controlled oscillator, enable input, complementary outputs | analog | 14 | ||
| 74x325 | 2 | dual voltage-controlled oscillator, complementary outputs | analog | 16 | ||
| 74x326 | 2 | dual voltage-controlled oscillator, enable input, complementary outputs | analog | 16 | ||
| 74x327 | 2 | dual voltage-controlled oscillator | analog | 14 | ||
| 74x330 | 1 | PLA | three-state | 20 | ||
| 74x331 | 1 | PLA | open-collector, 2.5 kΩ pull-up | 20 | ||
| 74x333 | 1 | PLA | three-state | 24 | ||
| 74x334 | 1 | PLA | three-state | 24 | ||
| 74x335 | 1 | PLA | open-collector | 24 | ||
| 74x336 | 1 | PLA | open-collector | 24 | ||
| 74x337 | 1 | clock driver | three-state | 20 | ||
| 74x340 | 8 | octal buffer, inverting outputs | Schmitt trigger | three-state | 20 | |
| 74x341 | 8 | octal buffer, non-inverting outputs | Schmitt trigger | three-state | 20 | |
| 74x344 | 8 | octal buffer, non-inverting outputs | Schmitt trigger | three-state | 20 | |
| 74x347 | 1 | BCD to 7-segment decoders/drivers, low voltage version of 7447 | open-collector | 16 | ||
| 74x348 | 1 | 8 to 3-line priority encoder | three-state | 16 | ||
| 74x350 | 1 | 4-bit shifter | three-state | 16 | ||
| 74x351 | 2 | dual 8-line to 1-line data selectors/multiplexers, 4 common data inputs | three-state | 20 | ||
| 74x352 | 2 | dual 4-line to 1-line data selectors/multiplexers, inverting outputs | 16 | |||
| 74x353 | 2 | dual 4-line to 1-line data selectors/multiplexers, inverting outputs | three-state | 16 | ||
| 74x354 | 1 | 8-line to 1-line data selector/multiplexer, transparent registers | three-state | 2 |