TI MSP430

The MSP430 is a mixed-signal microcontroller family from Texas Instruments, first introduced on 14 February 1992. Built around a CPU, the MSP430 was designed for low power consumption, embedded applications and low cost.

Features

The fundamental feature of the MSP430 is low power consumption. The first MSP430s had a consumption around 400 uA/MHz and less than 2 uA in low-power mode with active basic timer and LCD driver. The more recent MSPs have active mode consumption around 100-120 uA/MHz and 500 nA in low-power mode with active RTC. The consumption of the CPU itself is less than 32 uA/MHz. The MSP430FR series, which use FRAM instead of a flash, also allow fast writing to a non-volatile memory without additional power requirements.
The MSP430s use up to seven different low-power modes. The wake-up times differ on the mode and MSP430 generation. The fastest MSP430-family processors have wake-up times under 1 microsecond.
The MSP430s can run up to 25 MHz, while register-to-register operations take 1 cycle per instruction. The MSP430 family has more than 550 types, not counted package variants. There are microcontrollers with 0.5–512 KB flash or 0.5–256 KB FRAM and up to 66 KB RAM.
The device comes in a variety of generations featuring the usual peripherals:

Internal oscillator,
Timer including pulse-width modulation,
Watchdog timer,
USART,
Serial Peripheral Interface bus,
Inter-Integrated Circuit,
Analog-to-digital converter options:
* 10/12/14-bit successive-approximation ADC
* 16/24-bit delta–sigma ADC
* internal analog comparator with digital timers
** Can measure resistor-capacitor slope charging time
Brownout reset circuitry.

Some less usual peripheral options include on-chip operational amplifiers for signal conditioning, 12-bit digital-to-analog converter, liquid crystal display driver, hardware multiplier, USB, and direct memory access for ADC results. Apart from some older erasable programmable read-only memory and high volume mask ROM versions, all of the devices are in-system programming enabled via Joint Test Action Group, a built in bootstrapping loader using UART such as RS-232, or USB on devices with USB support. No BSL is included in F20xx, G2xx0, G2xx1, G2xx2, or I20xx family devices.

Memory limitations

There are, however, limits that preclude its use in more complex embedded systems. The MSP430 does not have an external memory bus, so it is limited to on-chip memory, up to 512 KB flash memory and 66 KB random-access memory, which may be too small for applications needing large buffers or data tables. Also, although it has a DMA controller, it is very difficult to use it to move data off the chip due to a lack of a DMA output strobe.

MSP430 CPU

Architecture

The MSP430 CPU uses a von Neumann architecture, with a single address space for instructions and data. Memory is byte-addressed, and pairs of bytes are combined little-endian to make 16-bit words.
The processor contains 16 16-bit registers, of which four are dedicated to special purposes: R0 is the program counter, R1 is the stack pointer, R2 is the status register, and R3 is a "constant generator" which reads as zero and ignores writes. Added address mode encodings using R3 and R2 allow a total of six commonly used constant values without needing an immediate operand word. R4 through R15 are available for general use.
The instruction set is very simple: 27 instructions exist in three categories. Most instructions occur in.B and.W suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to.W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.
The 10-bit signed jump offset is stored as a word displacement. The offset is doubled before being added to the PC. 16-bit jumps can be implemented with a MOV or ADD instruction

Instruction set

Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit source addressing mode and the 1-bit destination addressing mode fields. Some special versions can be constructed using R0, and modes other than register direct using R2 and R3 are interpreted specially. As Ad is only 1-bit, it can specify only a subset of the addressing modes for As.
Indexed addressing modes add a 16-bit extension word to the instruction. If both source and destination are indexed, the source extension word comes first. x refers to the next extension word in the instruction stream in the table below.
Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.
The MSP430X extension with 20-bit addressing adds added instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.
Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC.
When R0 or R1 are used with the autoincrement addressing mode, they are always incremented by two. Other registers are incremented by the operand size, either 1 or 2 bytes.
The status register contains four arithmetic status bits, a global interrupt enable, and four bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.

Pseudo-operations

Many added instructions are implemented as aliases for forms of the above. For example, there is no specific "return from subroutine" instruction, but it is implemented as MOV @SP+,PC. Emulated instructions are:

Emulated	Actual	Description
ADC.x ''dst	ADDC.x'' #0,dst	Add carry to destination
BR dst	MOV dst,PC	Branch to destination
CLR.x ''dst	MOV.x'' #0,dst	Clear destination
CLRC	BIC #1,SR	Clear carry bit
CLRN	BIC #4,SR	Clear negative bit
CLRZ	BIC #2,SR	Clear zero bit
DADC.x ''dst	DADD.x'' #0,dst	Decimal add carry to destination
DEC.x ''dst	SUB.x'' #1,dst	Decrement
DECD.x ''dst	SUB.x'' #2,dst	Double decrement
DINT	BIC #8,SR	Disable interrupts
EINT	BIS #8,SR	Enable interrupts
INC.x ''dst	ADD.x'' #1,dst	Increment
INCD.x ''dst	ADD.x'' #2,dst	Double increment
INV.x ''dst	XOR.x'' #−1,dst	Invert
NOP	MOV #0,R3	No operation
POP dst	MOV @SP+,dst	Pop from stack
RET	MOV @SP+,PC	Return from subroutine
RLA.x ''dst	ADD.x'' dst,''dst	Rotate left arithmetic
RLC.x'' dst	ADDC.x ''dst,dst	Rotate left through carry
SBC.x'' dst	SUBC.x #0,dst	Subtract borrow from destination
SET.x ''dst	MOV.x'' #-1,dst	Set destination
SETC	BIS #1,SR	Set carry bit
SETN	BIS #4,SR	Set negative bit
SETZ	BIS #2,SR	Set zero bit
TST.x ''dst	CMP.x'' #0,dst	Test destination

Note that the immediate constants −1, 0, 1, 2, 4 and 8 can be specified in a single-word instruction without needing a separate immediate operand.

MSP430X 20-bit extension

The basic MSP430 cannot support more memory than its 64K address space. In order to support this, an extended form of the MSP430 uses 20-bit registers and a 20-bit address space, allowing up to 1 MB of memory. This uses the same instruction set as the basic form, but with two extensions:

A limited number of 20-bit instructions for common operations, and
A general prefix word mechanism that can extend any instruction to 20 bits.

The extended instructions include some added abilities, notably multibit shifts and multiregister load/store operations.
20-bit operations use the length suffix "A" instead of.B or.W..W is still the default. In general, shorter operations clear the high-order bits of the destination register.
The new instructions are as follows:
All other instructions can have an prefix word added which extends them to 20 bits. The prefix word contains an added operand size bit, which is combined with the existing B/W bit to specify the operand size. One unused size combination exists; indications suggest that it may be used in future for a 32-bit operand size.
The prefix word comes in two formats, and the choice between them depends on the instruction which follows.
If the instruction has any non-register operands, then the simple form is used, which provides two 4-bit fields to extend any offset or immediate constant in the instruction stream to 20 bits.
If the instruction is register-to-register, a different extension word is used. This includes a "ZC" flag which suppresses carry-in, and a repeat count. A 4-bit field in the extension word encodes either a repeat count, or a register number which contains a 4-bit repeat count.