SDS Sigma series

The SDS Sigma series is a series of third generation computers that were introduced by Scientific Data Systems of the United States in 1966.
The first machines in the series are the 16-bit Sigma 2 and the 32-bit Sigma 7; the Sigma 7 was the first 32-bit computer released by SDS. At the time, the only competition for the Sigma 7 in the scientific space was the IBM System/360.
The Sigma 5, 6, 7, 8 and 9 were word addressed systems, memory sizes are stated in K. For example, the Sigma 5 base memory is 16K. Maximum physical memory is not limited by the length of the instruction address field of 17 bits, or 128K because the effective address could be augmented using memory mapping. Due to the width of the map registers, the maximum physical memory was 512K.
The CII 10070 computer was a rebadged Sigma 7 and served as a basis for the upgraded, yet still compatible, Iris 50 and Iris 80 computers. The Xerox 500 series computers, introduced starting in 1973, were also compatible upgrades to the Sigma systems using newer technology.
In 1975, Xerox sold its computer business to Honeywell, Inc. which continued support for the Sigma line for a time.
The Sigma 9 may hold the record for the longest lifetime of a machine selling near the original retail price. Sigma 9 computers were still in service in 1993. In 2011, the Living Computer Museum in Seattle, Washington acquired a Sigma 9 from a service bureau and has made it operational. That Sigma 9 CPU was at the University of Southern Mississippi until November 1985 when Andrews University purchased it and took it to Michigan. In February 1990, Andrews University via Keith Calkins sold and delivered it to Applied Esoterics in Flagstaff, Arizona. Keith Calkins made the Sigma 9 functional for the museum in 2012/2013 and brought up the CP-V operating system in December 2014. The various other system components came from other user sites, such as Marquette, Samford and Xerox/Dallas.

Models

Source:

32-bit systems

Model	Date	Floating point	Decimal	Byte string	Memory map	Max memory
Sigma 7	1966	optional	optional	standard	optional	128
Sigma 5	1967	optional	N/A	N/A	N/A	128
Sigma 6	1970	optional	standard	standard	standard	128
Sigma 9	1971	standard	standard	standard	standard	512
Sigma 8	1972	standard	N/A	N/A	N/A	128
Sigma 9 model 2	1972	standard	standard	standard	standard	256
Sigma 9 model 3	1973	standard	N/A	N/A	standard	512

16-bit systems

Instruction format

The format for memory-reference instructions for the 32-bit Sigma systems is as follows:


 +-+--------------+--------+------+---------------------------+
 |*| Op Code | R | X | Reference address |
 +-+--------------+--------+------+---------------------------+
bit 0 1 7 8 1 1 1 1 3
 1 2 4 5 1
Bit 0 indicates indirect address.
Bits 1-7 contain the operation code 
Bits 8-11 encode a register operand 
Bits 12-14 encode an index register. 0 indicates no indexing.
Bits 16-31 encode the address of a memory word.

For the Sigma 9, when real extended addressing is enabled, the reference address field is interpreted differently depending on whether the high-order bit is 0 or 1:


 +-+--------------+--------+------+-+-------------------------+
 | | | | |0| Address in 1st 64K words|
 |*| Op Code | R | X +-+-------------------------+
 | | | | |1| Low 16 bits of address |
 +-+--------------+--------+------+-+-------------------------+
bit 0 1 7 8 1 1 1 1 1 3
 1 2 4 5 6 1

If the high-order bit is 0, the lower 16 bits of the address refer to a location in the first 64K words of main memory; if the high-order bit is 1, the lower 16 bits of the address refer to a location in a 64K-word block of memory specified by the Extension Address in bits 42-47 of the Program Status Doubleword, with the Extension Address being concatenated with the lower 16 bits of the reference address to form the word address.
The word address from the instruction has two zero bits appended to it to calculate a byte address.
For instructions that refer to bytes, bits 13-31 of the index register are added to the byte address to form the effective address.
For instructions that refer to halfwords, bits 14-31 of the index register have a 0 bit appended to it, and that value is added to the byte address to form the effective address; the low-order bit of that address is always 0.
For instructions that refer to words, bits 15-31 of the index register have two 0 bits appended to it, and that value is added to the byte address to form the effective address; the low-order two bits of that address are always 0.
For instructions that refer to doublewords, bits 16-31 of the index register have three 0 bits appended to it, and that value is added to the byte address to form the virtual address; the low-order three bits of that address are always 0.

Features

CPU

Sigma systems provided a range of performance, roughly doubling from Sigma 5, the slowest, to Sigma 9 Model 3, the fastest. For example, 32-bit fixed point multiply times ranged from 7.2 to 3.8 μs; 64-bit floating point divide ranged from 30.5 to 17.4 μs.
Most Sigma systems included two or more blocks of 16 general-purpose registers. Switching blocks is accomplished by a single instruction, providing fast context switching, since registers do not have to be saved and restored.

Memory

Memory in the Sigma systems can be addressed as individual bytes, halfwords, words, or doublewords.
All 32-bit Sigma systems except the Sigma 5 and Sigma 8 used a memory map to implement virtual memory. The following description applies to the Sigma 9, other models have minor differences.
The effective virtual address of a word is 17 bits wide. Virtual addresses 0 thru 15 are reserved to reference the corresponding general purpose register, and are not mapped. Otherwise, in virtual memory mode the high-order eight bits of an address, called virtual page number, are used as an index to an array of 256 13-bit memory map registers. The thirteen bits from the map register plus the remaining nine bits of the virtual address form the address used to access real memory.
Access protection is implemented using a separate array of 256 two-bit access control codes, one per virtual page, indicating a combination of read/write/execute or no access to that page.
Independently, an array of 256 2-bit access control registers for the first 128k words of real memory function as a "lock-and-key" system in conjunction with two bits in the program status doubleword. The system allows pages to be marked "unlocked", or the key to be a "master key". Otherwise the key in the PSD had to match the lock in the access register in order to reference the memory page.

Diagnostic facilities

All the frames were powered by a PT16B power supply which took HF power input from a PT14/PT15 pair mounted on the rear frame rack. The PT16s could be margined by a switch to increase or decrease voltages by 5% in order to amplify failing components. The control panel also had a switch to allow increasing or decreasing basic clock rate for the same reason. These were for use by maintenance staff.
The Sigma 9 also had a series of registers called "SNAP" registers. The collected the status of various internal registers in the system at each clock tick. The major CPU diagnostics, for example 9Auto, 9Suffix) which tested various instructions, were supplied with a 9-track tape containing "Snap Data". This allowed the diagnostic, on an error detection, to run the instruction in "Snap Mode" which allowed the system to repeat the instruction one CPU phase at a time and collect the real data in the snap registers and compare it with correct example snap data from the snap tape. In this way an engineer could quickly see where a register bit was failing, amongst some other failure types.

Peripherals

Input/output is accomplished using a control unit called an IOP. An IOP provides an 8-bit data path to and from memory. Systems support up to 8 IOPs, each of which can attach up to 32 device controllers.
An IOP can be either a selector I/O processor or a multiplexer I/O processor. The SIOP provides a data rate up to 1.5 megabytes per second, but allows only one device to be active at a time. The MIOP, intended to support slow speed peripherals allows up to 32 devices to be active at any time, but provides only a.3 MBPS aggregate data rate.

Mass storage

The primary mass storage device, known as a RAD, contains 512 fixed heads and a large vertically mounted disk spinning at relatively low speeds. Because of the fixed head arrangement, access is quite fast. Capacities range from 1.6 to 6.0 megabytes and are used for temporary storage. Large-capacity multi-platter disks are employed for permanent storage.

Device	Device type	Capacity	Avg seek time	Avg rotational delay	Avg transfer rate
3214	RAD	2.75	N/A	8.5	647
7202	RAD	.7	N/A	17	166
7203	RAD	1.4	N/A	17	166
7204	RAD	2.8	N/A	17	166
7232	RAD	6.0	N/A	17	355
3231	Cartridge disk	2.4 removable	38	12.5	246
3232	Cartridge disk	4.9 removable	38	12.5	246
3233	Cartridge disk	4.9 fixed 4.9 removable	38	12.5	246
3242	Cartridge disk	5.7 removable	38	12.5	286
3243	Cartridge disk	5.7 fixed 5.7 removable	38	12.5	286
7251	Cartridge disk	2.3 removable	38	12.5	225
7252	Cartridge disk	2.3 fixed 2.3 removable	38	12.5	225
3277	Removable disk	95	30	8.3	787
7271	Removable disk	46.8	35	12.5	245