RISC-V
RISC-V is a free and open standard instruction set architecture based on reduced instruction set computer principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties.
RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981. In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025.
RISC-V is a popular architecture for microcontrollers and embedded systems, with development of higher-performance implementations targeting mobile, desktop, and server markets ongoing. The ISA is supported by several major Linux distributions, and companies such as SiFive, Andes Technology, SpacemiT, Synopsys, Alibaba, StarFive, Espressif Systems, and Raspberry Pi offer commercial systems on a chip and microcontrollers that incorporate one or more RISC-V compatible processor cores.
History
The term RISC dates from about 1980. Before then, there was some knowledge that simpler computers can be effective, but the design principles were not widely described. Simple, effective computers have always been of academic interest, and resulted in the RISC instruction set DLX for the first edition of Computer Architecture: A Quantitative Approach in 1990 of which David Patterson was a co-author, and he later participated in the RISC-V origination. DLX was intended for educational use; academics and hobbyists implemented it using field-programmable gate arrays, but it was never truly intended for commercial deployment.Krste Asanović at the University of California, Berkeley, had a research requirement for an open-source CPU core, and in 2010, he decided to develop and publish his own, in a "short, three-month project over the summer" with several of his graduate students. Several established open-source alternatives were available, but Asanović chose not to use them. ARM and SuperH CPUs had public-domain instruction sets with VHDL implementation files, while complete OpenRISC, OpenPOWER, and OpenSPARC / LEON cores were also available either as VHDL files or from various vendors. All of these existing options were supported by the GNU Compiler Collection, a popular free-software compiler, and had Linux kernel support. The plan was to aid both academic and industrial users. David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC, and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects at the University of California, Berkeley. At this stage, students provided initial software, simulations, and CPU designs.
The RISC-V authors and their institution originally sourced the ISA documents and several CPU designs under BSD licenses, which allow derivative works—such as RISC-V chip designs—to be either open and free, or closed and proprietary. The ISA specification itself was published in 2011 as open source, with all rights reserved. The actual technical report was later placed under a Creative Commons license to permit enhancement by external contributors through the RISC-V Foundation, and later RISC-V International.
A full history of RISC-V has been published on the RISC-V International website.
Foundations
Commercial users require an ISA to be stable before they can use it in a product that may last many years. To address this issue, the RISC-V Foundation was formed in 2015 to own, maintain, and publish intellectual property related to RISC-V's definition. The original authors and owners have surrendered their rights to the foundation. The foundation was led by CEO Calista Redmond, who took on the role in 2019 after leading open infrastructure projects at IBM. In 2024 she resigned as CEO.The founding members of RISC-V were: Andes Technology, Antmicro, Bluespec, Ceva, Codasip, Cortus, Esperanto Technologies, Espressif Systems, ETH Zurich, Google, IBM, ICT, IIT Madras, Lattice Semiconductor, LowRISC, Microchip Technology, the MIT Computer Science and Artificial Intelligence Laboratory, Qualcomm, Rambus, Rumble Development, SiFive, Syntacore and Technolution.
In November 2019, the RISC-V Foundation announced that it would relocate to Switzerland, citing concerns over U.S. trade regulations. As of March 2020, the organization was named RISC-V International, a Swiss nonprofit business association.
, RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the trademarked compatibility logo.
The Linux Foundation Europe started the RISC-V Software Ecosystem initiative on May 31, 2023. The goal of RISE is to increase the availability of software for high-performance and power-efficient RISC-V processors running high-level operating systems for a range of market segments by bringing together a large number of hardware and software vendors. Red Hat, Samsung, Qualcomm, Nvidia, MediaTek, Intel, and Google are among the initial members.
Awards
- 2017: The Linley Group's Analyst's Choice Award for Best Technology
Rationale
RISC-V was begun with a goal to make a practical ISA that was open-sourced, usable academically, and deployable in any hardware or software design without royalties. Also, justifying rationales for each design decision of the project are explained, at least in broad terms. The RISC-V authors are academics who have substantial experience in computer design, and the RISC-V ISA is a direct development from a series of academic computer-design projects, especially Berkeley RISC. RISC-V was originated in part to aid all such projects.
To build a large, continuing community of users and thereby accumulate designs and software, the RISC-V ISA designers intentionally support a wide variety of practical use cases: compact, performance, and low-power real-world implementations without over-architecting for a given microarchitecture. The requirements of a large base of contributors is part of the reason why RISC-V was engineered to address many possible uses.
The designers' primary assertion is that the instruction set is the key interface in a computer as it is situated at the interface between the hardware and the software. If a good instruction set were open and available for use by all, then it can dramatically reduce the cost of software by enabling far more reuse. It should also trigger increased competition among hardware providers, who can then devote more resources toward design and less for software support.
The designers maintain that new principles are becoming rare in instruction set design, as the most successful designs of the last forty years have grown increasingly similar. Of those that failed, most did so because their sponsoring companies were financially unsuccessful, not because the instruction sets were technically poor. Thus, a well-designed open instruction set designed using well-established principles should attract long-term support by many vendors.
RISC-V also encourages academic usage. The simplicity of the integer subset permits basic student exercises, and is a simple enough ISA to enable software to control research machines. The variable-length ISA provides room for instruction set extensions for both student exercises and research, and the separated privileged instruction set permits research in operating system support without redesigning compilers. RISC-V's open intellectual property paradigm allows derivative designs to be published, reused, and modified.
ISA base and extensions
RISC-V has a modular design, consisting of alternative base parts, with added optional extensions. The ISA base and its extensions are developed in a collective effort between industry, the research community and educational institutions. The base specifies instructions, control flow, registers, memory and addressing, logic manipulation, and ancillaries. The base alone can implement a simplified general-purpose computer, with full software support, including a general-purpose compiler.Standard extensions
The standard extensions are specified to work with all of the standard bases, and with each other without conflict.Many RISC-V computers might implement the compressed instructions extension, C, to reduce power consumption, code size, and memory use. There are also future plans to support hypervisors and virtualization.
Together with the supervisor extension, S, an RVG instruction set, which includes one of the RV base instruction sets, and the G collection of extensions, defines all instructions needed to conveniently support a general purpose operating system.
To name the combinations of functions that may be implemented, a nomenclature is defined to specify them in Chapter 27 of the current ratified Unprivileged ISA Specification. The instruction set base is specified first, coding for RISC-V, the register bit-width, and the variant; e.g., or. Then follows letters specifying implemented extensions, in the order of the above table. Each letter may be followed by a major optionally followed by "p" and a minor option number. It defaults to 0 if a minor version number is absent, and 1.0 if all of a version number is absent. Thus may be written as or more simply as. Underscores may be used between extensions for readability, for example.
The base, extended integer & floating-point calculations, with synchronization primitives for multi-core computing, are considered to be necessary for general-purpose computing, and thus we have the shorthand, "G".
A small 32-bit computer for an embedded system might be. A large 64-bit computer might be ; i.e.,.
With the growth in the number of extensions, the standard now provides for extensions to be named by a single "Z" followed by an alphabetical name and an optional version number. For example, names the instruction-fetch extension. and name version 2.0 of the same. The first letter following the "Z" by convention indicates the most closely related alphabetical extension category,. Thus the Zam extension for misaligned atomics relates to the "A" standard extension. Unlike single character extensions, Z extensions must be separated by underscores, grouped by category and then alphabetically within each category. For example,.
Extensions specific to supervisor privilege level are named in the same way using "S" for prefix. Extensions specific to hypervisor level are named using "H" for prefix. Machine level extensions are prefixed with the three letters "Zxm". Supervisor, hypervisor and machine level instruction set extensions are named after less privileged extensions.
RISC-V developers may create their own non-standard instruction set extensions. These follow the "Z" naming convention, but with "X" as the prefix. They should be specified after all standard extensions, and if multiple non-standard extensions are listed, they should be listed alphabetically.