Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications
Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications is a scholarly work, published in 2019 in ''Journal of Circuits, Systems and Computers''. The main subjects of the publication include power, logic gate, low-power electronics, arithmetic, electronic engineering, Power–delay product, algorithm, approximation error, nanoelectronics, dissipation, flexibility, fault tolerance, CMOS, binary adder, and computer science. The paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s).