PlayStation technical specifications

The PlayStation technical specifications describe the various components of the original PlayStation video game console.

Central processing unit (CPU)

LSI CoreWare CW33000-based core

MIPS R3000A-compatible 32-bit Reduced [instruction set computer|RISC] CPU MIPS R3051 with 5 KB L1 cache, running at 33.8688 MHz.
The microprocessor was manufactured by LSI Logic Corp. with technology licensed from SGI.
Features:
* Initial feature size was 0.5 micron.
* 850k – 1M transistors
* Operating performance: 30 MIPS
* Bus bandwidth 132 MB/s
* One arithmetic/logic unit
* One shifter
CPU cache RAM:
* 4 KB instruction cache
* 1 KB data cache configured as a scratchpad

Geometry Transformation Engine

Coprocessor that resides inside the main CPU processor, giving it additional vector math instructions used for 3D graphics, lighting, geometry, polygon and coordinate transformations – GTE performs high-speed matrix multiplications.
Operating performance: 66 MIPS
Uses fixed point arithmetic, different operations used different representations
Polygons per second :
* 90,000 with texture mapping, lighting and Gouraud shading
* 180,000 with texture mapping
* 360,000 with flat shading

Motion Decoder

Also residing within the main CPU, enables full screen, high quality FMV playback and is responsible for decompressing images and video into VRAM.
Operating performance: 80 MIPS
Documented device mode is to read three RLE-encoded 16×16 macroblocks, run IDCT and assemble a single 16×16 RGB macroblock.
Output data may be transferred directly to GPU via DMA.
It is possible to overwrite IDCT matrix and some additional parameters, however MDEC internal instruction set was never documented.
It is directly connected to a CPU bus.

System Control Coprocessor

This unit is part of the CPU. Has 16 32-bit control registers.
Modified from the original R3000A cop0 architecture, with the addition of a few registers and functions.
Controls memory management through virtual memory technique, system interrupts, exception handling, and breakpoints.

32-bit Sony GPU

Handles display of graphics, control of framebuffer, and drawing of polygons and textures
Handles 2D graphics processing, in a similar manner to the 3D engine
RAM:
* 1 MB VRAM for framebuffer
* 2 KB texture cache
* 64 bytes FIFO buffer
Features:
* Adjustable framebuffer
* Emulation of simultaneous backgrounds
* Mask bit
* Texture window
* Dithering
* Clipping
* Alpha blending
* Fog
* Framebuffer effects
* Transparency effects
* Render to texture
* Offscreen rendering
* Multipass rendering
* Flat or Gouraud shading and texture mapping
* No line restriction
* Colored light sourcing
Resolutions:
* Progressive: 256×224 to 640×240 pixels
* Interlaced: 256×448 to 640×480 pixels
Colors:
* Maximum color depth of 16,777,216 colors
* 57,344 to 153,600 colors on screen
* Unlimited color lookup tables
* 32 levels of transparency
* All calculations are performed to 24 bit accuracy
Texture mapping color mode:
* Mode 4: 4-bit CLUT
* Mode 8: 8-bit CLUT
* Mode 15: 15-bit direct
* Mode 24: 24-bit
Sprite engine
* 1024×512 framebuffer, 8×8 and 16×16 sprite sizes, bitmap objects
* Up to 4,000 sprites on screen, scaling and rotation
* 256×256 maximum sprite size
Special sprite effects:
* Rotation
* Scaling up/down
* Warping
* Transparency
* Fading
* Priority
* Vertical and horizontal line scroll
Pixel fillrate :
* 66 MPixel/s flat shaded polygons
* 33 MPixel/s Gouraud shaded polygons
* 33 MPixel/s for textured polygons with optional Gourard shading
* Actual fill rate is lower due to polygon overhead or texture cache misses

16-bit Sony SPU

CD-ROM drive

Two control pads via connectors

Backup flash RAM support

Two removable cards
Each card has 128 KB flash memory
OS support for File Save, Retrieve and Remove
Some games can use Memory Cards as main RAM, to store data for real time processing, bypassing the 2MB RAM limit.

Video and audio connectivity

Serial and parallel ports

Power input