Phase-locked loop


A phase-locked loop is a control system that generates an output signal whose phase is fixed relative to the phase of an input signal. Keeping the input and output phase in lockstep also implies keeping the input and output frequencies the same; thus, a phase-locked loop can also track an input frequency. Furthermore, by incorporating a frequency divider, a PLL can generate a stable frequency that is a multiple of the input frequency.
These properties are used for clock synchronization, demodulation, frequency synthesis, clock multipliers, and signal recovery from a noisy communication channel. Since 1969, a single integrated circuit can provide a complete PLL building block, and nowadays has output frequencies from a fraction of a hertz up to many gigahertz. Thus, PLLs are widely employed in radio, telecommunications, computers, grid-tie inverters, and other electronic applications.

Simple example

A simple analog PLL is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal with frequency proportional to an applied voltage, hence the term voltage-controlled oscillator. The phase detector compares the phase of the VCO's output signal with the phase of periodic input reference signal and outputs a voltage to adjust the oscillator's frequency to match the phase of to the phase of.

Clock analogy

Phase can be proportional to time, so a phase difference can correspond to a time difference.
Left alone, different clocks will mark time at slightly different rates. A mechanical clock, for example, might be fast or slow by a few seconds per hour compared to a reference atomic clock. That time difference becomes substantial over time. Instead, the owner can synchronize their mechanical clock by phase-locking it to a reference clock. An inefficient synchronization method involves the owner resetting their clock to that more accurate clock's time every week. But, left alone, their clock will still continue to diverge from the reference clock at the same few seconds per hour rate.
A more efficient synchronization method utilizes the fast-slow timing adjust control available on some clocks. Analogously to the phase comparator, the owner could notice their clock's misalignment and turn its timing adjust a small proportional amount to make their clock's frequency a little slower or faster. If they don't overcompensate, then their clock will be more accurate than before. Over a series of such weekly adjustments, their clock's notion of a second would agree close enough with the reference clock, so they could be said to be locked both in frequency and phase.
An early electromechanical version of a phase-locked loop was used in 1921 in the Shortt-Synchronome clock.

History

Spontaneous synchronization of weakly coupled pendulum clocks was noted by the Dutch physicist Christiaan Huygens as early as 1673. Around the turn of the 19th century, Lord Rayleigh observed synchronization of weakly coupled organ pipes and tuning forks. In 1919, W. H. Eccles and J. H. Vincent found that two electronic oscillators that had been tuned to oscillate at slightly different frequencies but that were coupled to a resonant circuit would soon oscillate at the same frequency. Automatic synchronization of electronic oscillators was described in 1923 by Edward Victor Appleton.
In 1925, David Robertson, first professor of electrical engineering at the University of Bristol, introduced phase locking in his clock design to control the striking of the bell Great George in the new Wills Memorial Building. Robertson's clock incorporated an electromechanical device that could vary the rate of oscillation of the pendulum, and derived correction signals from a circuit that compared the pendulum phase with that of an incoming telegraph pulse from Greenwich Observatory every morning at 10:00 GMT. Including equivalents of every element of a modern electronic PLL, Robertson's system was notably ahead of its time in that its phase detector was a relay logic implementation of the transistor circuits for phase/frequency detectors not seen until the 1970s.
Robertson's work predated research towards what was later named the phase-lock loop in 1932, when British researchers developed an alternative to Edwin Armstrong's superheterodyne receiver, the Homodyne or direct-conversion receiver. In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original modulation information. The intent was to develop an alternative receiver circuit that required fewer tuned circuits than the superheterodyne receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction signal was applied to the oscillator, maintaining it in the same phase and frequency of the desired signal. The technique was described in 1932, in a paper by Henri de Bellescize, in the French journal L'Onde Électrique.
In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronization pulses in the broadcast signal.
In 1969, Signetics introduced a line of low-cost monolithic integrated circuits like the NE565 using bipolar transistors, which were complete phase-locked loop systems on a chip, and applications for the technique multiplied. A few years later, RCA introduced the CD4046 Micropower Phase-Locked Loop using CMOS, which also became a popular integrated circuit building block.

Structure and function

Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure.
Analog PLL circuits include four basic elements:
There are several variations of PLLs. Some terms that are used are "analog phase-locked loop", also referred to as a linear phase-locked loop", "digital phase-locked loop", "all digital phase-locked loop", and "software phase-locked loop".
; Analog or linear PLL :Phase detector is an analog multiplier. Loop filter is active or passive. Uses a voltage-controlled oscillator. APLL is said to be a type II if its loop filter has transfer function with exactly one pole at the origin.
; Digital PLL : An analog PLL with a digital phase detector. May have a digital divider in the loop.
; All digital PLL : Phase detector, filter and oscillator are digital. Uses a numerically controlled oscillator.
; Neuronal PLL : Phase detector is implemented by neuronal non-linearity, oscillator by rate-controlled oscillating neurons.
; Software PLL : Functional blocks are implemented by software rather than specialized hardware.
; Charge-pump PLL :CP-PLL is a modification of phase-locked loops with phase-frequency detector and square waveform signals. See also Gardner's conjecture on CP-PLL.

Performance parameters

Phase-locked loops are widely used for synchronization purposes; in space communications for coherent demodulation and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.
Other applications include:
  • Demodulation of frequency modulation : If PLL is locked to an FM signal, the VCO tracks the instantaneous frequency of the input signal. The filtered error voltage, which controls the VCO and maintains lock with the input signal, is demodulated FM output. The VCO transfer characteristics determine the linearity of the demodulated out. Since the VCO used in an integrated-circuit PLL is highly linear, it is possible to realize highly linear FM demodulators.
  • Demodulation of frequency-shift keying : In digital data communication and computer peripherals, binary data is transmitted by means of a carrier frequency which is shifted between two preset frequencies.
  • Recovery of small signals that otherwise would be lost in noise
  • Recovery of clock timing information from a data stream, such as from a disk drive
  • Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections, while maintaining precise timing relationships
  • Demodulation of modems and other tone signals for telecommunications and remote control.
  • DSP of video signals; Phase-locked loops are also used to synchronize phase and frequency to the input analog video signal so it can be sampled and digitally processed
  • Atomic force microscopy in frequency modulation mode, to detect changes of the cantilever resonance frequency due to tip–surface interactions
  • DC motor drive

    Clock recovery

Some data streams, especially high-speed serial data streams, are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then uses a PLL to phase-align it to the data stream's signal edges. This process is referred to as clock recovery. For this scheme to work, the data stream must have edges frequently enough to correct any drift in the PLL's oscillator. Thus, a line code with a hard upper bound on the maximum time between edges is typically used to encode the data.