Performance Characterization and Majority Gate Design for MESO-Based Circuits
Performance Characterization and Majority Gate Design for MESO-Based Circuits is a scholarly work by Sachin Sapatnekar, published in 2018 in ''IEEE Journal on Exploratory Solid-State Computational Devices and Circuits''. The main subjects of the publication include logic family, pass transistor logic, logic synthesis, electronic circuit, logic gate, skyrmion, inverter, electronic engineering, ferroelectric random-access memory, generalization, computation, CMOS, Logic optimization, computer science, and computer engineering. The paper explores the application of the basic MESO device concept to more complex logic structures.