Management Component Transport Protocol
Management Component Transport Protocol is a protocol designed by the Distributed Management Task Force to support communications between different intelligent hardware components that make up a platform management subsystem, providing monitoring and control functions inside a managed computer system. This protocol is independent of the underlying physical bus properties, as well as the data link layer messaging used on the bus. The MCTP communication model includes a message format, transport description, message exchange patterns, and operational endpoint characteristics.
MCTP allows the transmission of a wide variety of management commands over alternative types of links. Simplified nature of the protocol and reduced encapsulation overheads make MCTP suitable for implementation and processing within system firmware and integrated baseboard management controllers, on a wide range of platforms – including servers, workstations and embedded devices. The following table describes which protocols MCTP can encapsulate, and what kind of protocols MCTP can be run over:
| Protocol | Can encapsulate | Can transmit over |
| PCI Express | ||
| NVM Express | ||
| CXL | ||
| Platform Level Data Model | ||
| NC-SI, Ethernet | ||
| USB | ||
| I2C/SMBus, I3C | ||
| Serial Port | ||
| ACPI PCC | ||
| UCIe | ||
For example, Intel's network interface controllers include support for MCTP over PCI Express and SMBus since 2012, allowing these NICs to be controlled and monitored at a low level over MCTP. Exposed configuration and monitoring operations include power management, control of Address Resolution Protocol offloading, configuration of the out-of-band management traffic, and handling of NIC's interrupts and error conditions.
DMTF also defines the Management Controller Host Interface, which includes a set of discovery options and registration commands, allowing UEFI, BIOS or the operating system to communicate with a MCTP-enabled BMC. Discovery options include PCI/PCI Express class codes as part of the PCI configuration space, MCHI Description Table and control methods defined and exported via ACPI, and data structures exported via SMBIOS.