MCST-R1000
The MCST R1000 is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by MCST.
During development this microprocessor was designated as MCST-4R.
MCST R1000 Highlights
- implements the SPARC V9 instruction set architecture
- quad-core
- core specifications:
- *in-order, dual-issue superscalar
- *7-stage integer pipeline
- *9-stage floating-point pipeline
- *VIS extensions 1 and 2
- *Multiply–accumulate unit
- *16 KB L1 instruction cache
- *32 KB L1 data cache
- *size 7.6 mm2
- shared 2MB L2 cache
- integrated memory controller
- integrated ccNUMA controller
- 1 GHz clock rate
- 90 nm process
- die size 128 mm2
- ~150 million transistors
- power consumption 15W
| [Image:MCST-4R core.gif|thumb|MCST R1000 core] | [Image:MCST-4R pipeline.gif|thumb|MCST R1000 pipeline] | [Image:MCST-4R diagram.gif|thumb|MCST R1000 diagram] | [Image:MCST-4R ccNUMA system.gif|thumb|ccNUMA multiprocessor system with four MCST R1000 microprocessors] |