List of Intel CPU microarchitectures

The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's tick–tock model, process–architecture–optimization model and Template:Intel processor roadmap.

x86 microarchitectures

16-bit">16-bit computing">16-bit

; 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. The 8088 version, with an 8-bit bus, was used in the original IBM Personal Computer.
; 186: included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
; 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The 80286 had a 24-bit address bus.

32-bit">32-bit computing">32-bit ([IA-32])

; i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
; i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit, 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
; P5: original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.
; P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
; NetBurst:commonly referred to as P7 although its internal name was P68. Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.

64-bit">64-bit computing">64-bit ([x86-64])

; Core (microarchitecture)|Core]: reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
; Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
; Sandy Bridge:32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007. First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers.
; Haswell: 22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and FMA.
; Skylake:14 nm microarchitecture, released August 5, 2015.
; Palm Cove: Originally meant to be successor to Skylake, but cancelled after releasing just one chip. Includes the AVX-512 instruction set.
; Sunny Cove:Successor to the Palm Cove core, first non-Atom core to include hardware acceleration for SHA hashing algorithms.
; Cypress Cove: Backport of Sunny Cove to Intel's 14 nm process
; Willow Cove:Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.
; Golden Cove:Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.
; Raptor Cove:A refresh of Golden Cove with increased L2 and L3 caches and core clocks.

x86 ULV">Ultra-low-voltage processor">ULV (Atom">Intel Atom">Atom)

;Bonnell
;Silvermont
;Goldmont
; Tremont:10 nm Atom microarchitecture iteration after Goldmont Plus.
;Gracemont

x86 MIC">Manycore processor">MIC (Many Integrated Core)

;Larrabee
;Xeon Phi

Other microarchitectures

[IA-64] ([Itanium])

; Merced: original Itanium microarchitecture. Used only in the first Itanium microprocessors.
; McKinley: enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor. Madison is the 130 nm version.
; Montecito: enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching and core-level lockstep execution.
; Tukwila: enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.
; Poulson: Itanium processor featuring an all-new microarchitecture. 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.
; Kittson: the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.

Miscellaneous

;4004/4040
;8008
;8080/8085
;iAPX 432
;80960
;80860
;XScale