Keshab K. Parhi


Keshab K. Parhi is an electrical engineer and computer scientist. He is currently the Erwin A. Kelen Chair in the department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. His research addresses architecture design of VLSI integrated circuit chips for signal processing, communications, artificial intelligence, and cryptosystems with a focus on reducing latency and increasing speed, while also reducing chip area and energy consumption. His research has also addressed neural engineering and DNA computing.
WWW ece.umn.edu/~parhi

Career

Parhi received the B. Tech. degree from the Indian Institute of Technology, Kharagpur in 1982, the M.S. degree from the University of Pennsylvania in 1984, and the Ph.D. degree from the University of California, Berkeley in 1988. He joined the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities in October 1988. He was promoted to Associate Professor with tenure in July 1992 and promoted to full professor in July 1995. From July 1997 to June 2022, he held the Edgar F. Johnson Professorship in Electronic Communication. Since July 2022, he holds the Erwin A. Kelen Chair in Electrical Engineering. From July 2008 to August 2011, he served as the Director of Graduate Studies of the Electrical Engineering Program.
Parhi has been a Visiting Professor at the Delft University of Technology, Lund University, Fudan University, and Stanford University. He has held short-term appointments at IBM T.J. Watson Research Center, Bell Laboratories, NEC C&C Laboratory, Broadcom Corporation, and Medtronic. From 2005 to 2012, he served as Founder, President, and Chief Scientist of Leanics Corp. Leanics was supported by SBIR funding from the National Science Foundation and the Department of Defense.

Research

Parhi’s interdisciplinary research in late 1980s advanced the field of VLSI signal processing by integrating concepts from computer architecture, digital signal processing, and VLSI design. In particular, he developed algorithm transformations techniques such as unfolding and folding for DSP programs described by iterative data-flow graphs.
His research has led to pipelined-parallel architectures for signal processing operations such as recursive and adaptive digital filters, decision-feedback equalizers, Tomlinson-Harashima precoders, parallel decision-feedback decoders, and fast Fourier transforms. He has developed architectures for modern error correction encoders/decoders including turbo codes, low-density parity-check codes, and polar codes. These technologies are found in numerous integrated circuit chips for physical-layer communications in wired and wireless media that form the backbone of the internet.
His research has led to high-speed architectures for cryptosystems such as the advanced encryption standard (AES), post-quantum cryptography, and homomorphic encryption. He has also developed approaches to obfuscating integrated circuits using keys to prevent the sale of excess parts and to protect key parameters of the design. In the 1990s, Parhi worked on a DARPA funded project on high-level synthesis that led to the development of the Minnesota Architecture Synthesis System for time-constrained and resource-constrained synthesis of data-flow graphs. His research group also developed the Hierarchical Energy Analysis Tool to estimate power consumption with circuit-simulation-level accuracy from logic-level simulation.

Literary works

Parhi has also authored over 725 papers and is inventor or co-inventor of 36 issued US patents.

Professional service

Parhi has served the Institute of Electrical and Electronics Engineers in various capacities. He has served as Associate Editor for numerous transactions published by the IEEE Circuits and Systems Society and the IEEE Signal Processing Society. His leadership roles include:

Distinctions and awards