International Symposium on Microarchitecture

The IEEE/ACM International Symposium on Microarchitecture^® is an annual academic conference on microarchitecture, generally viewed as the top-tier academic conference on computer architecture. It is not to be confused with a micro-conference. Particularly within the domains of microarchitecture and Code generation (compiler), MICRO is unrivaled and esteemed as the premier forum. Association for Computing Machinery's Special Interest Group on Microarchitecture and Institute of Electrical and Electronics Engineers Computer Society are technical sponsors.
MICRO Hall of Fame provides a list of the most prolific authors at the ISCA conference, spanning contributions starting from the first ISCA conference in 1973.

MICRO Test of Time (ToT) Award

The SIGMICRO Test of Time Award recognizes influential papers from prior editions of the International Symposium on Microarchitecture. It was first awarded in 2014 and has since been awarded annually, typically to papers published years prior to the award year.
; Recent and past recipients

2024 : Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches — Moinuddin K. Qureshi; Yale N. Patt.
2023 : Orion: A Power-Performance Simulator for Interconnection Networks — Hang-Sheng Wang; Xinping Zhu; Li-Shiuan Peh; Sharad Malik.
2022 : A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor — Shubhendu S. Mukherjee; Christopher T. Weaver; Joel S. Emer; Steven K. Reinhardt; Todd M. Austin.
2022 : Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data — Canturk Isci; Margaret Martonosi.
2021 : Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation — Dan Ernst; Nam Sung Kim; Shidhartha Das; Sanjay Pant; Rajeev R. Rao; Toan Pham; Conrad H. Ziesler; David T. Blaauw; Todd M. Austin; Krisztián Flautner; Trevor N. Mudge.
2021 : Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction — Rakesh Kumar; Keith I. Farkas; Norman P. Jouppi; Parthasarathy Ranganathan; Dean M. Tullsen.
2020 : A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality — Zhao Zhang; Zhichun Zhu; Xiaodong Zhang.
2020 : Fetch Directed Instruction Prefetching — Glenn Reinman; Brad Calder; Todd M. Austin.
2020 : A Dynamic Multithreading Processor — Haitham Akkary; Michael A. Driscoll.
2019 : Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution — Ravi Rajwar; James R. Goodman.
2019 : Selective Cache Ways: On-Demand Cache Resource Allocation — David H. Albonesi.
2018 : DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design — Todd M. Austin.
2018 : Assigning Confidence to Conditional Branch Predictions — Erik Jacobsen; Eric Rotenberg; James E. Smith.
2018 : Efficient Path Profiling — Thomas Ball; James R. Larus.
2017 : Exceeding the Dataflow Limit Via Value Prediction — Mikko H. Lipasti; John Paul Shen.
2016 : Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops — B. Ramakrishna Rau.
2015 : Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching — Eric Rotenberg; Steve Bennett; James E. Smith.
2014.