List of Intel graphics processing units


This article contains information about Intel's GPUs and motherboard graphics chipsets in table form. In 1982, Intel licensed the NEC μPD7220 and announced it as the Intel 82720 Graphics Display Controller.

Gen1

Intel's first generation GPUs:

Gen2

Intel marketed its second generation using the brand Extreme Graphics. These chips added support for texture combiners allowing support for OpenGL 1.3.

Gen3

Intel's first DirectX 9 GPUs with hardware Pixel Shader 2.0 support.

Gen4

The last generation of motherboard integrated graphics. Full hardware DirectX 10 support starting with GMA X3500.
  • Each EU has a 128-bit wide FPU that natively executes four 32-bit operations per clock cycle.

    Gen5

  • Integrated graphics chip moved from motherboard into the processor.
  • Improved gaming performance
  • Can access CPU's cache
  • Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.
  • Hierarchical-Z compression and fast Z clear

    Gen6

  • Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.
  • Double peak performance per clock cycle compared to previous generation due to fused multiply-add instruction.
  • The entire GPU shares a sampler and an ROP.

    Gen7

  • 1 FP32 ALUs : EUs : Subslices
  • Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
  • Each Subslice contains 6 or 8 EUs and a sampler, and has 64 KB shared memory.

    Gen7.5

  • 1 FP32 ALUs : EUs : Subslices
  • Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
  • Each Subslice contains 6 or 8 EUs and a sampler, and has 64 KB shared memory.

    Gen8

  • 1 FP32 ALUs : EUs : Subslices
  • Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 FLOPS is twice the FP32 FLOPS. Since the throughput of FP64 instructions is one per 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
  • Each Subslice contains 8 EUs and a sampler, and has 64 KB shared memory.
  • Intel Quick Sync Video
  • For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.

    Gen9

  • 1 FP32 ALUs : EUs : Subslices
  • Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 FLOPS is twice the FP32 FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
  • Each Subslice contains 8 EUs and a sampler, and has 64 KB shared memory.
  • Intel Quick Sync Video
  • For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
  • WDDM 2.2 support with Windows Mixed Reality begins with KabyLake-based GPUs.

    Gen11

  • 1 FP32 ALUs : EUs : Subslices
  • Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 FLOPS is twice the FP32 FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
  • Each Subslice contains 8 EUs and a sampler, and has 64 KB shared memory.
  • Intel Quick Sync Video
  • For Windows 10, the total system memory that is available for graphics use is half the system memory.
  • No eDRAM.

    Gen12

is a GPGPU and dGPU product line first released in 2020, in the mobile Tiger Lake line and Rocket Lake line.
  • 1 FP32 ALUs: EUs: Subslices

    Gen12.2

is a GPGPU and dGPU product line first released in 2021, in Alder Lake and Raptor Lake line.
  • Support up to 4 screens
  • 1 FP32 ALUs: EUs: Subslices

    Gen 12.5

Gen 12.7

Desktop

Mobile

Workstation

Battlemage based

Desktop

Workstation

PowerVR based

Larrabee based

Larrabee is the codename for a cancelled GPGPU chip that Intel was developing separately from its current line of integrated graphics accelerators. It is named after either Mount Larrabee or Larrabee State Park in the state of Washington. The chip was to be released in 2010 as the core of a consumer 3D graphics card, but these plans were cancelled due to delays and disappointing early performance figures. The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010 and its technology was passed on to the Xeon Phi. The Intel MIC multiprocessor architecture announced in 2010 inherited many design elements from the Larrabee project, but does not function as a graphics processing unit; the product is intended as a co-processor for high performance computing.