Intel MCS-51


The Intel MCS-51 is a single-chip microcontroller series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton. Intel's original versions were popular in the 1980s and early 1990s, and enhanced binary compatible derivatives remain popular today. It is a complex instruction set computer with separate memory spaces for program instructions and data.
Intel's original MCS-51 family was developed using N-type metal–oxide–semiconductor technology, like its predecessor Intel MCS-48, but later versions, identified by a letter C in their name use complementary metal–oxide–semiconductor technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices.
The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/16/32-bit MCS-251 family of binary compatible microcontrollers. While Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family, enhanced binary compatible derivatives made by numerous vendors remain popular today. Some derivatives integrate a digital signal processor or a floating-point unit. Beyond these physical devices, several companies also offer MCS-51 derivatives as IP cores for use in field-programmable gate array or application-specific integrated circuit designs.

Important features and applications

The 8051 architecture provides many functions, random-access memory, read-only memory, input/output in one package:
One feature of the 8051 core is the inclusion of a Boolean processing engine, which allows bit-level Boolean logic operations to be carried out directly and efficiently on select internal registers, ports and select RAM locations. Another feature is the inclusion of four bank-selectable working register sets, which greatly reduce the time required to perform the context switches to enter and leave interrupt service routines. With one instruction, the 8051 can switch register banks, avoiding the time-consuming task of transferring the critical registers to RAM.

Derivative features

, new derivatives are still being developed by many major chipmakers, and major compiler suppliers such as IAR Systems, Keil and TASKING continuously release updates.
MCS-51-based microcontrollers typically include one or two UARTs, two or three timers, 128 or 256 bytes of internal data RAM, up to 128 bytes of I/O, 512 bytes to 64 KB of internal program memory, and sometimes a quantity of extended data RAM located in the external data space. External RAM and ROM share the data and address buses. The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle and have clock frequencies of up to 100 MHz, thus being capable of an even greater number of instructions per second. All Silicon Labs, some Dallas and a few Atmel devices have single-cycle cores.
8051 variants may include built-in reset timers with brown-out detection, on-chip oscillators, self-programmable flash ROM program memory, built-in external RAM, extra internal program storage, bootloader code in ROM, EEPROM non-volatile data storage, I2C, SPI, and USB host interfaces, CAN or LIN bus, Zigbee or Bluetooth radio modules, PWM generators, analog comparators, analog-to-digital and digital-to-analog converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, extra power-saving modes, more or fewer parallel ports etc. Intel manufactured a mask-programmed version, 8052AH-BASIC, with a BASIC interpreter in ROM, capable of running user programs loaded into RAM.
MCS-51-based microcontrollers have been adapted to extreme environments. Examples for high-temperature variants are the Tekmos TK8H51 family for −40°C to +250°C or the Honeywell HT83C51 for −55°C to +225°C. Radiation-hardenend MCS-51 microcontrollers for use in spacecraft are available; e.g., from Cobham as the UT69RH051 or from NIIET as the 1830VE32.
In some engineering schools, the 8051 microcontroller is used in introductory microcontroller courses.

Family naming conventions

Intel's first MCS-51 microcontroller was the 8051, with 4 KB ROM and 128 byte RAM. Variants starting with 87 have a user-programmable EPROM, sometimes UV-erasable. Variants with a C as the third character are some kind of CMOS. 8031 and 8032 are ROM-less versions, with 128 and 256 bytes of RAM. The last digit can indicate memory size, e.g. 8052 with 8 KB ROM, 87C54 16 KB EPROM, and 87C58 with 32 KB EPROM, all with 256-byte RAM.

Memory architecture

The MCS-51 has four distinct types of memory: internal RAM, special function registers, program memory, and external data memory. To access these efficiently, some compilers utilize as many as 7 types of memory definitions: internal RAM, single-bit access to internal RAM, special function registers, single-bit access to selected special function registers, program RAM, external RAM accessed using a register indirect access, using one of the standard 8-bit registers, and register indirect external RAM access utilizing the 16-bit indirect access register.
The 8051's instruction set is designed as a Harvard architecture with segregated memory ; it can only execute code fetched from program memory and has no instructions to write to program memory. However, the bus leaving the IC has a single address and data path, and strongly resembles a von Neumann architecture bus.
Most 8051 systems respect the instruction set and require customized features to download new executable programs, e.g. in flash memory.

Internal RAM

has an 8-bit address space, using addresses 0 through 0xFF. IRAM from 0x00 to 0x7F contains 128 directly addressable 1-byte registers, which can be accessed using an 8-bit absolute address that is part of the instruction. Alternatively, IRAM can be accessed indirectly: the address is loaded into R0 or R1, and the memory is accessed using the @R0 or @R1 syntax, or as stack memory through the stack pointer SP, with the PUSH/POP and *CALL/RET operations.
The original 8051 has only 128 bytes of IRAM. The 8052 added IRAM from 0x80 to 0xFF, which can only be accessed indirectly. Most 8051 clones also have a full 256 bytes of IRAM.
Direct accesses to the IRAM addresses 0x80–0xFF are, instead, mapped onto the special function registers, where the accumulators A, B, carry bit C, and other special registers for control, status, etc., are located.

Special function registers

Special function registers are located in the same address space as IRAM, at addresses 0x80 to 0xFF, and are accessed directly using the same instructions as for the lower half of IRAM. They cannot be accessed indirectly via @R0 or @R1 or by the stack pointer SP; indirect access to those addresses will access the second half of IRAM instead.
The special function registers include the accumulators A and B and program status word, themselves, as well as the 16-bit data pointer DPTR. In addition to these, a small core of other special function registers including the interrupt enable IE at A8 and interrupt priority IP at B8; the I/O ports P0, P1, P2, P3 ; the serial I/O control SCON and buffer SBUF ; the CPU/power control register PCON ; and the registers for timers 0 and 1 control and operation mode, the 16-bit timer 0 and timer 1 are present on all versions of the 8051. Other addresses are version-dependent; in particular, the registers of timer 2 for the 8052, the control register T2CON, the 16-bit capture/latch and timer 2 are not included with the 8051.

Register windows

The 32 bytes in IRAM from 0x00 to 0x1F contain space for four 8-byte register windows, which the eight registers R0–R7 map to. The currently active window is determined by a two-bit address contained in the program status word.

Bit registers

The 16 bytes at IRAM locations 0x20–0x2F contain space for 128 1-bit registers, which are separately addressable as bit registers 00–7F.
The remaining bit registers, addressed as 80–FF, are mapped onto the 16 special function registers 80, 88, 90, 98, ..., F0 and F8, and therefore include the bits comprising the accumulators A, B and program status word PSW. The register window address, being bits 3 and 4 of the PSW, is itself addressable as bit registers D3 and D4 respectively; while the carry bit C, at bit 7 of the PSW, is addressable as bit register D7.

Program memory

Program memory is up to 64 KB of read-only memory, starting at address 0 in a separate address space. It may be on- or off-chip, depending on the particular model of chip being used. Program memory is read-only, though some variants of the 8051 use on-chip flash memory and provide a method of re-programming the memory in-system or in-application.
In addition to code, it is possible to store read-only data such as lookup tables in program memory, retrieved by the or instructions. The address is computed as the sum of the 8-bit accumulator and a 16-bit register.
Special jump and call instructions slightly reduce the size of code that accesses local program memory.
When code larger than 64 KB is required, a common system makes the code bank-switched, with general-purpose I/O selecting the upper address bits. Some 8051 compilers make provisions to automatically access paged code. In these systems, the interrupt vectors and paging table are placed in the first 32 KB of code and are always resident.