IBM System/370-XA


IBM System/370-XA is an instruction set architecture announced by IBM on October 21, 1981 for the IBM 308X processors and available in April 1983. It extends the IBM System/370 architecture to support 31-bit virtual and physical addresses, and includes a redesigned I/O architecture.

31-bit virtual addressing

In the System/360 and System/370 architectures, the general-purpose registers were 32 bits wide, the machine performed 32-bit arithmetic operations, and addresses were always stored in 32-bit words. For this reason, the 360 and 370 architectures are 32-bit architectures.
However, other than the 360/67, the implementation of these machines ignored the top 8 bits of the address, resulting in 24-bit addressing. Such limitations were not uncommon in computer architectures in the era when physical memory was normally measured in kilobytes. This was reflected in some parts of the instruction set, for instance one heavily used instruction,, Load Address, explicitly cleared the top eight bits of the address being placed in a register. Much of System/360's and System/370's large installed code base relied on a 24-bit logical address and if the 24-bit limit were to be removed, this would create migration problems for existing software.
This was addressed by adding an addressing mode bit to the Program Status Word controlling whether the program runs in 24-bit mode, in which the top eight bits of virtual addresses are ignored, or 31-bit mode, in which only the uppermost bit of virtual addresses are ignored. Several reasons were given for the choice of 31 bits instead of 32 bits:
  1. The desire to retain the high-order bit as a "control or escape bit." In particular, the standard subroutine calling convention marked the final parameter word by setting its high bit.
  2. Interaction between 32-bit addresses and two loop control instructions, and that treated their arguments as signed numbers when doing comparisons.
  3. Input from key initial Model 67 sites, which had debated the alternatives during the initial system design period, and had recommended 31 bits.
Certain machine instructions in this 31-bit addressing mode alter the addressing mode bit. For example, the original subroutine call instructions, Branch and Link, and its register-register equivalent,, Branch and Link Register, store certain status information, the instruction length code, the condition code and the program mask, in the top byte of the return address. A, Branch and Save, instruction was added to allow 31-bit return addresses., and its register-register equivalent,, Branch and Save Register, was part of the instruction set of the 360/67, which was the only System/360 model to allow addresses longer than 24 bits. These instructions were maintained, but were modified and extended for 31-bit addressing.
Additional instructions in support of allowing calls between 24-bit-addressing and 31-bit-addressing code include two new register-register call/return instructions which also effect an addressing mode change,, Branch and Save and Set Mode, the 24/31-bit version of a call where the linkage address including the mode is saved and a branch is taken to an address in a possibly different mode, and, Branch and Set Mode, the 24/31 bit version of a return, where the return is directly to the previously saved linkage address and in its previous mode. Taken together, and allow 24-bit calls to 31-bit, 31-bit calls to 24-bit, 24-bit calls to 24-bit and 31-bit calls to 31-bit.
Like, is used as, where the linkage address and mode are saved in register 14, and a branch is taken to the subroutine address and mode specified in register 15. Somewhat similarly to, is used as, where 0 indicates that the current mode is not saved, and a return to the caller at the address and mode specified in register 14 is to be taken.

31-bit physical addressing

System/370 initially supported only 24-bit physical addresses; the extended real address feature extended this to 26-bit addresses.
System/370-XA changed the page table entry format to support 19 bits of page frame address; pages are 4 KB in 370-XA, so combining a 19-bit page frame address with a 12-bit offset within the page produces a 31-bit physical address. Channel command words can be in one of two formats, with format 0 being the System/370 format, with a 24-bit data address, and format 1 being an additional format, with a 31-bit data address.

I/O

System/370-XA introduced a major redesign of the I/O architecture, shifting responsibility from the operating system into a new channel subsystem:

Channel subsystem

  • Performed I/O queuing previously handled by the OS
  • Improved concurrency and efficiency
  • Reduced CPU overhead for managing I/O paths
  • Provided improved fault isolation and recovery

Key components

Subchannels: Logical representations of I/O devices, replacing earlier device control block modelsPath management: Support for dynamic selection of I/O paths to improve availabilityI/O interruption architecture: Streamlined signaling from I/O channels to CPUs

Benefits

  • Higher throughput for high-volume transaction systems
  • Better scalability as installations grew
  • Allowed operating systems like MVS/XA to manage large-scale enterprise workloads more efficiently