Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches is a scholarly work, published in 2018 in ''International Journal of Grid and Utility Computing''. The main subjects of the publication include semiconductor device reliability, error detection and correction, CPU cache, computer science, magnetoresistive random-access memory, cache, ferroelectric random-access memory, parallel computing, soft error, clustered file system, embedded system, and skyrmion. In this paper, the vulnerability of STT-MRAM caches has been investigated to examine the effect of workloads as well as process variations for characterising the reliability of STT-MRAM cache.