Digital clock manager

A digital clock manager is an electronic component available on some field-programmable gate arrays . A digital clock manager is useful for manipulating clock signals inside the FPGA, and to avoid clock skew which would introduce errors in the circuit.

Uses

Digital clock managers have the following applications:

Multiplying or dividing an incoming clock.
Making sure the clock has a steady duty cycle.
Adding a phase shift with the additional use of a delay-locked loop.
Eliminating clock skew within an FPGA design.