Control register

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

History

The early CPU lacked dedicated control registers, and relied on a limited set of internal signals and flags. When IBM developed a paging version of the System/360, they added 16 control registers to the design for what became the 360/67. IBM did not provide control registers on other S/360 models, but made them a standard part of System/370, although with different register and bit assignments. As IBM added new features to the architecture, e.g., DAS, S/370-XA, S/370-ESA, ESA/390, they added additional fields to the control registers. With z/Architecture, IBM doubled the control register size to 64 bits.

Control registers in IBM 360/67

On the 360/67, CR0 and CR2 are used by address translation, CR 4-6 contain miscellaneous flags including interrupt masks and Extended Control Mode, and CR 8-14 contain the switch settings on the 2167 Configuration Unit.

M67 CR0

Control Register 0 contains the address of the segment table for dynamic address translation.

M67 CR2

Control register 2 is the Relocation exception address register.

M67 CR4

CR4 is the extended mask register for channels 0-31.
Each bit is the 1/0 channel mask for the corresponding channel.

M67 CR5

CR5 is reserved for the extended mask register for channels 32–63.
Each bit is the 1/0 channel mask for the corresponding channel.

M67 CR6

CR6 contains two mode flags plus extensions to the PSW mask bits.

Field	Bit	Description
0	0	Machine Check Mask Extension for Channel Controller o
1	1	Machine Check Mask Extension for Channel Controller 1
2-3		Reserved for channel controllers 2-3
4-7		Unassigned
8	8	Extended Control Mode
9	9	Configuration Control Bit
10-23		Unassigned
24-31		External interrupt masking
	24	Timer
	25	Interrupt Key
	26	Malfunction Alert - CPU 1
	27	Malfunction Alert - CPU 2
	28	Reserved
	29	Reserved
	30	External Interrupt - CPU 1, 2
	31	Reserved

M67 CR8

Control Register 8 contains the assignments of Processor Storage units 1–4 to central processing units and channel controllers.

Bit	Description
0	Processor Storage Unit 1 to CPU 1
1	Processor Storage Unit 1 to CPU 2
2-3	Reserved for CPU 3-4
4	Processor Storage Unit 1 to CC 0
5	Processor Storage Unit 1 to CC 1
6-7	Reserved for CC 3-4
8	Processor Storage Unit 2 to CPU 1
9	Processor Storage Unit 2 to CPU 2
10-11	Reserved for CPU 3-4
12	Processor Storage Unit 2 to CC 0
13	Processor Storage Unit 2 to CC 1
14-15	Reserved for CC 3-4
16	Processor Storage Unit 3 to CPU 1
17	Processor Storage Unit 3 to CPU 2
18-19	Reserved for CPU 3-4
20	Processor Storage Unit 3 to CC 0
21	Processor Storage Unit 3 to CC 1
22-23	Reserved for CC 3-4
24	Processor Storage Unit 4 to CPU 1
25	Processor Storage Unit 4 to CPU 2
26-27	Reserved for CPU 3-4
28	Processor Storage Unit 4 to CC 0
29	Processor Storage Unit 4 to CC 1
30-31	Reserved for CC 3-4

M67 CR9

Control Register 9 contains the assignments of Processor Storage units 5–8 to central processing units and channel controllers.

Bit	Description
0	Processor Storage Unit 5 to CPU 1
1	Processor Storage Unit 5 to CPU 2
2-3	Reserved for CPU 3-4
4	Processor Storage Unit 5 to CC 0
5	Processor Storage Unit 5 to CC 1
6-7	Reserved for CC 3-4
8	Processor Storage Unit 6 to CPU 66
9	Processor Storage Unit 6 to CPU 2
10-11	Reserved for CPU 3-4
12	Processor Storage Unit 6 to CC 0
13	Processor Storage Unit 6 to CC 1
14-15	Reserved for CC 3-4
16	Processor Storage Unit 7 to CPU 1
17	Processor Storage Unit 7 to CPU 2
18-19	Reserved for CPU 3-4
20	Processor Storage Unit 7 to CC 0
21	Processor Storage Unit 7 to CC 1
22-23	Reserved for CC 3-4
24	Processor Storage Unit 8 to CPU 1
25	Processor Storage Unit 8 to CPU 2
26-27	Reserved for CPU 3-4
28	Processor Storage Unit 8 to CC 0
29	Processor Storage Unit 8 to CC 1
30-31	Reserved for CC 3-4

M67 CR10

Control Register 10 contains the Processor storage address assignment codes.

Bit	Starting Address Code for
0-3	Processor Storage Unit 1
4-7	Processor Storage Unit 2
8-11	Processor Storage Unit 3
12-15	Processor Storage Unit 4
16-19	Processor Storage Unit 5
20-23	Processor Storage Unit 6
24-27	Processor Storage Unit 7
28-31	Processor Storage Unit 8

M67 CR11

Control Register 11 contains channel controller assignments.

Bit	Description
0	CC 0 available on CPU 1
1	CC 0 available on CPU 2
2-3	Reserved for CPUs 3-4
4	CC 1 available on CPU 1
5	CC 1 available on CPU 2
6-7	Reserved for CPUs 3-4
8-15	Unassigned
16	CPU 1 to only CC 0
17	CPU 1 to only CC 1
18-19	Reserved for CC 2-3
20	CPU 2 to only CC 0
21	CPU 2 to only CC 1
22-23	Reserved for CC 2-3
24-31	Unassigned

M67 CR12

CR12 contains I/O Control Unit Partitioning.

Bit	I/O Control Unit	Interface
0	1	1
1	1	2
2	2	1
3	2	2
4	3	1
5	3	2
6	4	1
7	4	2
8	5	1
9	5	2
10	6	1
11	6	2
12	7	1
13	7	2
14	8	1
15	8	2
16	9	1
17	9	2
18	10	1
19	10	2
20	11	1
21	11	2
22	12	1
23	12	2
24	13	1
25	13	2
26	14	1
27	14	2
28	15	1
29	15	2
30	16	1
31	16	2

M67 CR13

CR13 contains I/O Control Unit Partitioning.

Bit	I/O Control Unit	Interface
0	17	1
1	17	2
2	18	1
3	18	2
4	19	1
5	19	2
6	20	1
7	20	2
8	21	1
9	21	2
10	22	1
11	22	2
12	23	1
13	23	2
14	24	1
15	24	2
16	25	1
17	25	2
18	26	1
19	26	2
20	27	1
21	27	2
22	28	1
23	28	2
24	29	1
25	29	2
26	30	1
27	30	2
28	31	1
29	31	2
30	32	1
31	32	2