A Fast-Lock Low-Jitter PLL Based Adaptive Bandwidth Technique
A Fast-Lock Low-Jitter PLL Based Adaptive Bandwidth Technique is a scholarly work, published in 2018 in ''Journal of Physics: Conference Series''. The main subjects of the publication include jitter, electronic engineering, electromagnetic compatibility, lock, control theory, biological robustness, bandwidth, PLL multibit, CMOS, phase-locked loop, delay-locked loop, and computer science. The PLL is implemented in a 65nm CMOS process, while the core occupies 0.05mm2 and measurement results shows that the adaptive bandwidth PLL can generate clock with frequency from 200MHz to 1.6GHz.