SIMM

A SIMM is a type of memory module used in computers from the early 1980s to the early 2000s. It is a printed circuit board upon which multiple random-access memory Integrated circuit chips are attached to one or both sides. It differs from a dual in-line memory module, the most predominant form of memory module since the late 1990s, in that the contacts on a SIMM are redundant on both sides of the module. SIMMs were standardised under the JEDEC JESD-21C standard.
Most early PC motherboards used socketed DIP chips for DRAM. As computer memory capacities grew, memory modules were used to save motherboard space and ease memory expansion. Instead of plugging in eight or nine single DIP chips, only one additional memory module was needed to increase the memory of the computer.

History

SIMMs were invented in 1983 by James E. Clayton at Wang Laboratories with subsequent patents granted in 1987.
Wang Laboratories litigated both patents against multiple companies. The original memory modules were built upon ceramic substrates with 64K Hitachi "flip chip" parts and had pins, i.e. single in-line package packaging. SIMMs using pins are usually called SIP or SIPP memory modules to distinguish them from the more common modules using edge connectors.
The first variant of SIMMs has 30 pins and provides 8 bits of data. They were used in AT-compatible, 386-based, 486-based, Macintosh Plus, Macintosh II, Quadra, Atari STE microcomputers, Wang VS minicomputers and Roland electronic samplers.
The second variant of SIMMs has 72 pins and provides 32 bits of data. These appeared first in the early 1990s in later models of the IBM PS/2, and later in systems based on the 486, Pentium, Pentium Pro, early Pentium II, and contemporary/competing chips of other brands. By the mid-90s, 72-pin SIMMs had replaced 30-pin SIMMs in new-build computers, and were starting to themselves be replaced by DIMMs.
Non-IBM PC computers such as UNIX workstations may use proprietary non-standard SIMMs. The Macintosh IIfx uses proprietary non-standard SIMMs with 64 pins.
DRAM technologies used in SIMMs include FPM, and the higher-performance EDO DRAM.
Due to the differing data bus widths of the memory modules and some processors, sometimes several modules must be installed in identical pairs or in identical groups of four to fill a memory bank. The rule of thumb is a 286, 386SX, 68000 or low-end 68020 / 68030 system would require two 30-pin SIMMs for a memory bank. On 386DX, 486, and full-spec 68020 through 68060 systems, either four 30-pin SIMMs or one 72-pin SIMM are required for one memory bank. On Pentium systems, two 72-pin SIMMs are required. However, some Pentium systems have support for a "half bank mode", in which the data bus would be shortened to only 32 bits to allow operation of a single SIMM. Conversely, some 386 and 486 systems use what is known as "memory interleaving", which requires twice as many SIMMs and effectively doubles the bandwidth.
The earliest SIMM sockets were conventional push-type sockets. These were soon replaced by ZIF sockets in which the SIMM was inserted at an angle, then tilted into an upright position. To remove one, the two metal or plastic clips at each end must be pulled to the side, then the SIMM must be tilted back and pulled out. The earlier sockets used plastic retainer clips which were found to break, so steel clips replaced them.
Some SIMMs support presence detect. Connections are made to some of the pins that encode the capacity and speed of the SIMM, so that compatible equipment can detect the properties of the SIMM. PD SIMMs can be used in equipment which does not support PD; the information is ignored. Standard SIMMs can easily be converted to support PD by fitting jumpers, if the SIMMs have solder pads to do so, or by soldering wires on.

30-pin SIMMs

Standard sizes: 256 KB, 1 MB, 4 MB, 16 MB.
30-pin SIMMs have 12 address lines, which can provide a total of 24 address bits. With an 8-bit data width, this leads to an absolute maximum capacity of 16 MB for both parity and non-parity modules.

Pin #	Name	Signal description	Pin #	Name	Signal description
1	V_CC	+5 VDC	16	DQ4	Data 4
2	/CAS	Column address strobe	17	A8	Address 8
3	DQ0	Data 0	18	A9	Address 9
4	A0	Address 0	19	A10	Address 10
5	A1	Address 1	20	DQ5	Data 5
6	DQ1	Data 1	21	/WE	Write enable
7	A2	Address 2	22	V_SS	Ground
8	A3	Address 3	23	DQ6	Data 6
9	V_SS	Ground	24	A11	Address 11
10	DQ2	Data 2	25	DQ7	Data 7
11	A4	Address 4	26	QP^*	Data parity out
12	A5	Address 5	27	/RAS	Row address strobe
13	DQ3	Data 3	28	/CASP^*	Parity column address strobe
14	A6	Address 6	29	DP^*	Data parity in
15	A7	Address 7	30	V_CC	+5 VDC

^* Pins 26, 28 and 29 are not connected on non-parity SIMMs.

72-pin SIMMs

Standard sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB
With 12 address lines, which can provide a total of 24 address bits, two ranks of chips, and 32-bit data output, the absolute maximum capacity is 2²⁷ = 128 MB.

Pin #	Name	Signal description	Pin #	Name	Signal description
1	V_SS	Ground	37	MDP1^*	Data parity 1
2	MD0	Data 0	38	MDP3^*	Data parity 3
3	MD16	Data 16	39	V_SS	Ground
4	MD1	Data 1	40	/CAS0	Column address strobe 0
5	MD17	Data 17	41	/CAS2	Column address strobe 2
6	MD2	Data 2	42	/CAS3	Column address strobe 3
7	MD18	Data 18	43	/CAS1	Column address strobe 1
8	MD3	Data 3	44	/RAS0	Row address strobe 0
9	MD19	Data 19	45	/RAS1^†	Row address strobe 1
10	V_CC	+5 VDC	46	NC	Not connected
11	NU	Not used	47	/WE	Read/write enable
12	MA0	Address 0	48	NC	Not connected
13	MA1	Address 1	49	MD8	Data 8
14	MA2	Address 2	50	MD24	Data 24
15	MA3	Address 3	51	MD9	Data 9
16	MA4	Address 4	52	MD25	Data 25
17	MA5	Address 5	53	MD10	Data 10
18	MA6	Address 6	54	MD26	Data 26
19	MA10	Address 10	55	MD11	Data 11
20	MD4	Data 4	56	MD27	Data 27
21	MD20	Data 20	57	MD12	Data 12
22	MD5	Data 5	58	MD28	Data 28
23	MD21	Data 21	59	V_CC	+5 VDC
24	MD6	Data 6	60	MD29	Data 29
25	MD22	Data 22	61	MD13	Data 13
26	MD7	Data 7	62	MD30	Data 30
27	MD23	Data 23	63	MD14	Data 14
28	MA7	Address 7	64	MD31	Data 31
29	MA11	Address 11	65	MD15	Data 15
30	V_CC	+5 VDC	66	NC	Not connected
31	MA8	Address 8	67	PD1^x	Presence detect 1
32	MA9	Address 9	68	PD2^x	Presence detect 2
33	/RAS3^†	Row address strobe 3	69	PD3^x	Presence detect 3
34	/RAS2	Row Address Strobe 2	70	PD4^x	Presence detect 4
35	MDP2^*	Data parity 2	71	NC	Not connected
36	MDP0^*	Data parity 0	72	V_SS	Ground

^* Pins 35, 36, 37 and 38 are not connected on non-parity SIMMs.

^† /RAS1 and /RAS3 are only used on two-rank SIMMS: 2, 8, 32, and 128 MB.

^# These lines are only defined on 3.3 V modules.

^x Presence-detect signals are detailed in JEDEC standard.