NX bit
The NX bit is a processor feature that separates areas of a virtual address space into sections for storing data or program instructions. An operating system supporting the NX bit can mark certain areas of the virtual address space as non-executable, preventing the processor from running any code stored there. This technique, known as executable space protection or Write XOR Execute, protects computers from malicious software that attempts to insert harmful code into another program’s data storage area and execute it, such as in a buffer overflow attack.
The term "NX bit" was introduced by Advanced Micro Devices as a marketing term. Intel markets this feature as the XD bit, while the MIPS architecture refers to it as the XI bit. In the ARM architecture, introduced in ARMv6, it is known as XN. The term NX bit is often used broadly to describe similar executable space protection technologies in other processors.
Architecture support
x86
processors, since the 80286, included a similar capability implemented at the segment level. However, almost all operating systems for the 80386 and later x86 processors implement the flat memory model, so they cannot use this capability. There was no "Executable" flag in the page table entry in those processors, until, to make this capability available to operating systems using the flat memory model, AMD added a "no-execute" or NX bit to the page table entry in its AMD64 architecture, providing a mechanism that can control execution per page rather than per whole segment.Intel implemented a similar feature in its Itanium processor—having IA-64 architecture—in 2001, but did not bring it to the more popular x86 processor families. In the x86 architecture it was first implemented by AMD, as the NX bit, for use by its AMD64 line of processors, such as the Athlon 64 and Opteron.
After AMD's decision to include this functionality in its AMD64 instruction set, Intel implemented the similar XD bit feature in x86 processors beginning with the Pentium 4 processors based on later iterations of the Prescott core. The NX bit specifically refers to bit number 63 of a 64-bit entry in the page table. If this bit is set to 0, then code can be executed from that page; if set to 1, code cannot be executed from that page, and anything residing there is assumed to be data. It is only available with the long mode or legacy Physical Address Extension page-table formats, but not x86's original 32-bit page table format because page table entries in that format lack the 64th bit used to disable and enable execution.
Windows XP SP2 and later support Data Execution Prevention.
ARM
In ARMv6, a new page table entry format was introduced; it includes an "execute never" bit. For ARMv8-A, VMSAv8-64 block and page descriptors, and VMSAv8-32 long-descriptor block and page descriptors, for stage 1 translations have "execute never" bits for both privileged and unprivileged modes, and block and page descriptors for stage 2 translations have a single "execute never" bit ; VMSAv8-32 short-descriptor translation table descriptors at level 1 have "execute never" bits for both privileged and unprivileged mode and at level 2 have a single "execute never" bit.Alpha
As of the Fourth Edition of the Alpha Architecture manual, DEC Alpha has a Fault on Execute bit in page table entries with the OpenVMS, Tru64 UNIX, and Alpha Linux PALcode.SPARC
The SPARC Reference MMU for Sun SPARC version 8 has permission values of Read Only, Read/Write, Read/Execute, and Read/Write/Execute in page table entries, although not all SPARC processors have a SPARC Reference MMU.A SPARC version 9 MMU may provide, but is not required to provide, any combination of read/write/execute permissions. A Translation Table Entry in a Translation Storage Buffer in Oracle SPARC Architecture 2011, Draft D1.0.0 has separate Executable and Writable bits.