Segment descriptor
In memory addressing for computer architectures, segment descriptors are a part of the segmentation unit, used for translating a logical address to a linear address or to the address of a page table. Segment descriptors describe the memory segment referred to in the logical address.
Structure
The segment descriptor contains the following fields:- A segment base address or page table address
- The segment limit which specifies the segment size
- Access rights information containing the protection mechanism information
- Control bits
Intel
The 80286 segment descriptor
The 80286 segment descriptor has the following form:The x86 and x86-64 segment descriptor
The x86 and x86-64 segment descriptor has the following form:What the fields stand for:
; Base Address : Starting memory address of the segment. Its length is 32 bits and it is created from the lower part bits 16 to 31, and the upper part bits 0 to 7, followed by bits 24 to 31.
; Segment Limit : Its length is 20 bits and is created from the lower part bits 0 to 15 and the upper part bits 16 to 19. It defines the address of the last accessible data. The length is one more than the value stored here. How exactly this should be interpreted depends on the Granularity bit of the segment descriptor.
; G=Granularity : If clear, the limit is in units of bytes, with a maximum of 220 bytes. If set, the limit is in units of 4096-byte pages, for a maximum of 232 bytes.
; D/B
; L=Long : If set, this is a 64-bit segment, and code in this segment uses the 64-bit instruction encoding. "L" cannot be set at the same time as "D" aka "B".
; AVL=Available : For software use, not used by hardware
; P=Present : If clear, a "segment not present" exception is generated on any reference to this segment
; DPL=Descriptor privilege level : Privilege level required to access this descriptor
; S=System Segment : If clear, this is system segment, used to handle interrupts or store LDT segment descriptors. If 1, this is Code/Data segment.
; Type: If set, this is a code segment descriptor. If clear, this is a data/stack segment descriptor, which has "D" replaced by "B", "C" replaced by "E"and "R" replaced by "W". This is in fact a special case of the 2-bit type field, where the preceding bit 12 cleared as "0" refers to more internal system descriptors, for LDT, LSS, and gates.
; C=Conforming : Code in this segment may be called from less-privileged levels.
; E=Expand-Down: If clear, the segment expands from base address up to base+limit. If set, it expands from maximum offset down to limit, a behavior usually used for stacks.
; R=Readable : If clear, the segment may be executed but not read from.
; W=Writable : If clear, the data segment may be read but not written to.
; A=Accessed : This bit is set to 1 by hardware when the segment is accessed, and cleared by software.
IBM S/370 and successors
The S/370, S/370-XA, ESA/370 and ESA/390 segment table entries are one word long. All processors running in S/370 mode used the same format, but not all supported the common-segment facility and the protected segment facility. XA introduced a new format and replaced segment protection with page protection.With z/Architecture the STE is a doubleword.
The S/370 segment-table entry
The segment-table entry for the S/370 has the following form; Page-Table Origin
;TBL
;P
;C
;I
The S/370-XA through S/390 segment-table entry
The segment-table entry for the S/370-XA, ESA/370 and ESA/390 has the following form; Page-Table Origin
;I
;C
;TBL
The z/Architecture segment-table entry
In the original z/Architecture, a segment is always subject to paging and the Segment-Table Entry always points to a page table. However, on a model equipped with the Enhanced-DAT Facility 1, the Enhanced-DAT-enablement control oThe segment-table entry for the z/Architecture has the following forms
; Page-Table Origin
; FC=0
; P
; I
; CS
; TT=00
; ACCF-Validity Control
; ACC
; F
; FC=1
; P
; Instruction-Execution-Protection Control
; I
; CS
; TT=00