Serial Peripheral Interface

Serial Peripheral Interface is a de facto standard for synchronous serial communication, used primarily in embedded systems for short-distance wired communication between integrated circuits.
SPI follows a master–slave architecture, where a master device orchestrates communication with one or more slave devices by driving the clock and chip select signals. Some devices support changing master and slave roles on the fly.
Motorola's original specification uses four logic signals, aka lines or wires, to support full duplex communication. It is sometimes called a four-wire serial bus to contrast with three-wire [|variants] which are half duplex, and with the two-wire I²C and 1-Wire serial buses.
Typical [|applications] include interfacing microcontrollers with peripheral chips for Secure Digital cards, liquid crystal displays, analog-to-digital and digital-to-analog converters, flash and EEPROM memory, and various communication chips.
Although SPI is a synchronous serial interface, it is different from Synchronous Serial Interface. SSI employs differential signaling and provides only a single simplex communication channel.

Operation

Commonly, SPI has four logic signals. [|Variations] may use different [|names] or have different signals.
MOSI on a master outputs to MOSI on a slave. MISO on a slave outputs to MISO on a master.
Each device internally uses a shift register for serial communication, which together forms an inter-chip circular buffer.
Slave devices should use tri-state outputs so their MISO signal becomes high impedance when the device is not selected. Slaves without tri-state outputs cannot share a MISO line with other slaves without using an external tri-state buffer.

Data transmission

To begin communication, the SPI master first selects a slave device by pulling its low.
If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.
During each SPI clock cycle, full-duplex transmission of a single bit occurs. The master sends a bit on the MOSI line while the slave sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.
Transmission using a single slave involves one shift register in the master and one shift register in the slave, both of some given word size. The transmissions often consist of eight-bit words, but other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters.
Data is usually shifted out with the most-significant bit first but the original specification has a LSBFE to control whether data is transferred least or most significant bit first. On the clock edge, both master and slave shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.
If a single slave device is used, its pin may be fixed to logic low if the slave permits it. With multiple slave devices, a [|multidrop configuration] requires an independent signal from the master for each slave device, while a [|daisy-chain configuration] only requires one signal.
Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent contention on MISO, non-selected slaves must use tristate output. Slaves that are not already tristate will need external tristate buffers to ensure this.

Clock polarity and phase

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola named these two options as CPOL and CPHA respectively, a convention most vendors have also adopted.
File:SPI timing diagram CS.svg|thumb|338x338px|SPI timing diagram for both clock polarities and phases. Data bits output on blue lines if CPHA=0, or on red lines if CPHA=1, and sample on opposite-colored lines. Numbers identify data bits. Z indicates high impedance.
The SPI timing diagram shown is further described below:

CPOL represents the polarity of the clock. Polarities can be converted with a simple inverter.
* SCLK is a clock which idles at the logical low voltage.
* SCLK is a clock which idles at the logical high voltage.
CPHA represents the phase of each data bit's transmission cycle relative to SCLK.
* For CPHA=0:
** The first data bit is output immediately when activates.
** Subsequent bits are output when SCLK transitions to its idle voltage level.
** Sampling occurs when SCLK transitions from its idle voltage level.
* For CPHA=1:
** The first data bit is output on SCLK's first clock edge after activates.
** Subsequent bits are output when SCLK transitions from its idle voltage level.
** Sampling occurs when SCLK transitions to its idle voltage level.
* Conversion between these two phases is non-trivial.
* MOSI and MISO signals are usually stable for the half cycle until the next bit's transmission cycle starts, so SPI master and slave devices may sample data at different points in that half cycle, for flexibility, despite the original specification.
Mode numbers

The combinations of polarity and phases are referred to by these "SPI mode" numbers with CPOL as the high order bit and CPHA as the low order bit:

SPI mode	Clock polarity	Clock phase	Data is shifted out on	Data is sampled on
0	0	0	falling SCLK, and when activates	rising SCLK
1	0	1	rising SCLK	falling SCLK
2	1	0	rising SCLK, and when activates	falling SCLK
3	1	1	falling SCLK	rising SCLK

Notes:

Another commonly used notation represents the mode as a tuple; e.g., the value '' would indicate CPOL=0 and CPHA=1.
In Full Duplex operation, the master device could transmit and receive with different modes. For instance, it could transmit in Mode 0 and be receiving in Mode 1 at the same time.
Different vendors may use different naming schemes, like CKE for clock edge or NCPHA for the inversion of CPHA.
Valid communications

Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access an IC's scan chain by issuing a command word of one size and then getting a response of a different size.

Interrupts

Interrupts are outside the scope of SPI; their usage is neither forbidden nor specified, and so may be implemented optionally.

From master to slave

Microcontrollers configured as slave devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive FIFO buffer, and may also set up an interrupt routine when their slave select input line is pulled low or high.

From slave to master

SPI slaves sometimes use an out-of-band signal to send an interrupt signal to a master. Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real-time clock chips, SDIO and audio jack insertions for an audio codec. Interrupts to master may also be faked by using polling.

Bus topologies

Though the previous operation section focused on a basic interface with a single slave, SPI can instead communicate with multiple slaves using multidrop, daisy chain, or expander configurations.

Multidrop configuration

In the multidrop bus configuration, each slave has its own, and the master selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used.
Since the MISO pins of the slaves are connected together, they are required to be tri-state pins, where the high-impedance output must be applied when the slave is not selected. Slave devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its signal.

Caveat: All signals should start high before sending initialization messages to any slave, so other uninitialized slaves ignore messages not addressed to them. This is a concern if the master uses general-purpose input/output pins for and if the master uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for to output a high voltage for all slaves before running initialization code from any of those software libraries. Another solution is to add a pull-up resistor on each, to ensure that all signals are initially high.

Daisy chain configuration

Some products that implement SPI may be connected in a daisy chain configuration, where the first slave's output is connected to the second slave's input, and so on with subsequent slaves, until the final slave, whose output is connected back to the master's input. This effectively merges the individual communication shift registers of each slave to form a single larger combined shift register that shifts data through the chain. This configuration only requires a single line from the master, rather than a separate line for each slave.
In addition to using SPI-specific slaves, daisy-chained SPI can include discrete shift registers for more pins of inputs or outputs chained indefinitely. Other applications that can potentially interoperate with daisy-chained SPI include SGPIO, JTAG, and I²C.