Power-on self-test
A power-on self-test is a process performed by firmware or software routines immediately after a computer or other digital electronic device is powered on.
POST processes may set the initial state of the device from firmware and detect if any hardware components are non-functional. The results of the POST may be displayed on a panel that is part of the device, output to an external device, or stored for future retrieval by a diagnostic tool. In some computers, an indicator lamp or a speaker may be provided to show error codes as a sequence of flashes or beeps in the event that a computer display malfunctions.
POST routines are part of a computer's pre-boot sequence. If they complete successfully, the bootstrap loader code is invoked to load an operating system.
In IBM PC compatible computers, the main duties of POST are handled by the BIOS or UEFI.
IBM-compatible PC POST
In IBM PC compatible computers, the main duties of POST are handled by the BIOS or UEFI, which may hand some of these duties to other programs designed to initialize very specific peripheral devices, notably for video and SCSI initialization. These other duty-specific programs are generally known collectively as option ROMs or individually as the video BIOS, SCSI BIOS, etc.History
In earlier BIOSes, up to around the turn of the millennium, the POST would perform a thorough test of all devices, including a complete memory test. This design by IBM was modeled after their larger mainframe systems, which would perform a complete hardware test as part of their cold-start process. As the PC platform evolved into more of a commodity consumer device, the mainframe and minicomputer-inspired high-reliability features such as parity memory and the thorough memory test in every POST were dropped from most models. The exponential growth of PC memory sizes, driven by the equally exponential drop in memory prices, was also a factor in this, as the duration of a memory test using a given CPU is directly proportional to the memory size.The original IBM PC could be equipped with as little as 16 KB of RAM and typically had between 64 and 640 KB; depending on the amount of equipped memory, the computer's 4.77 MHz 8088 required between 5 seconds and 1.5 minutes to complete the POST and there was no way to skip it. Beginning with the IBM XT, a memory count was displayed during POST instead of a blank screen. A modern PC with a bus rate of around 1 GHz and a 32-bit bus might be 2000x or even 5000x faster, but might have many more gigabytes of memory. With boot times more of a concern now than in the 1980s, the 30- to 60-second memory test adds undesirable delay for a benefit of confidence that is not perceived to be worth that cost by most users. Most clone PC BIOSes allowed the user to skip the POST RAM check by pressing a key, and more modern machines often performed no RAM test at all unless it was enabled via the BIOS setup. In addition, modern DRAM is significantly more reliable than DRAM was in the 1980s.
Purposes
During the POST, the BIOS must integrate multiple competing, changing, and even mutually exclusive standards and initiatives for the matrix of hardware and operating systems the PC is expected to support, although at most only simple memory tests and the setup screen are displayed. The principal duties of the main BIOS during POST include:- verify CPU registers
- verify the integrity of the BIOS code itself
- verify some basic components like DMA, timer, interrupt controller
- initialize, size, and verify system main memory
- initialize BIOS
- pass control to other specialized extension BIOSes
- identify, organize, and select which devices are available for booting
- initialize chipset
- discover, initialize, and catalog all system buses and devices
- provide a user interface for system's configuration
- construct whatever system environment is required by the target operating system
Process
The BIOS begins its POST when the CPU is reset. The first memory location the CPU tries to execute is known as the reset vector. In the case of a hard reboot, the northbridge will direct a code fetch request to the BIOS located on the system flash memory. For a warm boot, the BIOS will be located in the proper place in RAM and the northbridge will direct the reset vector call to the RAM. In earlier PC systems, before chipsets were standard, the BIOS ROM would be located at an address range that included the reset vector, and BIOS ran directly out of ROM. This is why the motherboard BIOS ROM is in segment F000 in the conventional memory map.During the POST flow of a contemporary BIOS, one of the first things a BIOS should do is determine the reason it is executing. For a cold boot, for example, it may need to execute all of its functionality. If, however, the system supports power saving or quick boot methods, the BIOS may be able to circumvent the standard POST device discovery, and simply program the devices from a preloaded system device table.
As part of the starting sequence the POST routines may display a prompt to the user for a key press to access built-in setup functions of the BIOS. This allows the user to set various options particular to the motherboard before the operating system is loaded. If no key is pressed, the POST will proceed on to the boot sequence required to load the installed operating system.
Many modern BIOS and UEFI implementations show a manufacturers logo during POST and hide the classic text screens unless an error occurs. The text screen can often be enabled in the BIOS settings by disabling the "Quiet Boot" option.
Progress and error reporting
The original IBM BIOS made POST diagnostic information available by outputting a number to I/O port 0x80. Both progress indication and error codes were generated; in the case of a failure which did not generate a code, the code of the last successful operation was available to aid in diagnosing the problem. Using a logic analyzer or a dedicated POST cardan interface card that shows port 0x80 output on a small displaya technician could determine the origin of the problem. Once an operating system is running on the computer the code displayed by such a board may become meaningless, since some OSes, e.g. Linux, use port 0x80 for I/O timing operations. The actual numeric codes for the possible stages and error conditions differ from one BIOS supplier to another. Codes for different BIOS versions from a single supplier may also vary, although many codes remain unchanged in different versions.Later BIOSes used a sequence of beeps from the motherboard-attached PC speaker to signal error codes. Some vendors developed proprietary variants or enhancements, such as MSI's D-Bracket. POST beep codes vary from manufacturer to manufacturer.
Information on numeric and beep codes is available from manufacturers of BIOSes and motherboards. There are websites which collect codes for many BIOSes.
Original IBM POST beep codes
POST AMI BIOS beep codes
| Beeps | Meaning |
| 1 | Memory refresh timer error |
| 2 | Parity error in base memory |
| 3 | Base memory read/write test error |
| 4 | Motherboard timer not operational |
| 5 | Processor failure |
| 6 | 8042 Gate A20 test error |
| 7 | General exception error |
| 8 | Display memory error |
| 9 | AMI BIOS ROM checksum fix |
| 10 | CMOS shutdown register read/write fix |
| 11 | Cache memory test failed |
| continuous beeping | Motherboard does not detect a RAM module |
POST beep codes on CompTIA A+ certification exam
These POST beep codes are covered specifically on the CompTIA A+ Exam:| Beeps | Meaning |
| Steady, short beeps | Power supply may be bad |
| Long continuous beep tone | Memory failure |
| Steady, long beeps | Power supply bad |
| No beep | Power supply bad, system not plugged in, or power not turned on |
| No beep | If everything seems to be functioning correctly there may be a problem with the 'beeper' itself. The system will normally beep one short beep. |
| One long, two short beeps | Video card failure |
IBM POST diagnostic code descriptions
| Code | Meaning |
| 100–199 | System boards |
| 200–299 | Memory |
| 300–399 | Keyboard |
| 400–499 | Monochrome display |
| 500–599 | Color/graphics display |
| 600–699 | Floppy-disk drive or adapter |
| 700–799 | Math coprocessor |
| 900–999 | Parallel printer port |
| 1000–1099 | Alternate printer adapter |
| 1100–1299 | Asynchronous communication device, adapter, or port |
| 1300–1399 | Game port |
| 1400–1499 | Color/graphics printer |
| 1500–1599 | Synchronous communication device, adapter, or port |
| 1700–1799 | Hard drive or adapter |
| 1800–1899 | Expansion unit |
| 2000–2199 | Bisynchronous communication adapter |
| 2400–2599 | system-board video |
| 3000–3199 | adapter |
| 4800–4999 | Internal modem |
| 7000–7099 | Phoenix BIOS chips |
| 7300–7399 | 3.5-inch disk drive |
| 8900–8999 | adapter |
| 11200–11299 | SCSI adapter |
| 21000–21099 | SCSI fixed disk and controller |
| 21500–21599 | SCSI CD-ROM system |