LatticeMico32
LatticeMico32 is a 32-bit microprocessor reduced [instruction set computer] soft core from Lattice Semiconductor optimized for field-programmable gate arrays. It uses a Harvard architecture, so the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.
LatticeMico32 is licensed under a free core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture. It is possible to embed a LatticeMico32 core into Xilinx and Altera FPGAs, in addition to the Lattice Semiconductor parts the LatticeMico32 was developed for. AMD PowerTune uses LatticeMico32.
The CPU core and the development toolchain are available as source-code, allowing third parties to implement changes to the processor architecture.
Features
- RISC load/store architecture
- 32-bit data path
- 32-bit fixed-size instructions
- 32 general purpose registers
- Up to 32 external interrupts
- Configurable instruction set including user defined instructions
- Optional configurable caches
- Optional pipelined memories
- Dual Wishbone memory interfaces
- Memory mapped I/O
- 6 stage pipeline
Toolchain
- GNU Compiler Collection – C/C++ compiler; LatticeMico32 support is added in GCC 4.5.0, patches are available for support in GCC 4.4.0
- Binutils – Assembler, linker, and binary utilities; supports LatticeMico32 since version 2.19
- GNU Debugger – Debugger
- Eclipse – Integrated development environment
- Newlib – C library
- μCos-II, μITRON, RTEMS - real-time operating systems
- μClinux – operating system