CPUID

In the x86 architecture, the CPUID instruction is a processor supplementary instruction allowing software to discover details of the processor. It was introduced by Intel in 1993 with the launch of the Pentium and late 486 processors.
A program can use the CPUID to determine processor type and whether features such as MMX/SSE are implemented.

History

Prior to the general availability of the CPUID instruction, programmers would write esoteric machine code which exploited minor differences in CPU behavior in order to determine the processor make and model. With the introduction of the 80386 processor, EDX on reset indicated the revision but this was only readable after reset and there was no standard way for applications to read the value.
Outside the x86 family, developers are mostly still required to use esoteric processes to determine the variations in CPU design that are present.
For example, in the Motorola 68000 series — which never had a CPUID instruction of any kind — certain specific instructions required elevated privileges. These could be used to tell various CPU family members apart. In the Motorola 68010 the instruction MOVE from SR became privileged. Because the 68000 offered an unprivileged MOVE from SR the two different CPUs could be told apart by a CPU error condition being triggered.
While the CPUID instruction is specific to the x86 architecture, other architectures often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86 CPUID instruction.

Calling CPUID

The CPUID opcode is 0F A2.
In assembly language, the CPUID instruction takes no parameters as CPUID implicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf. CPUID should be called with EAX = 0 first, as this will store in the EAX register the highest EAX calling parameter that the CPU implements.
To obtain extended function information CPUID should be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, call CPUID with EAX = 80000000h.
CPUID leaves greater than 3 but less than 80000000 are accessible only when the model-specific registers have IA32_MISC_ENABLE.BOOT_NT4 = 0. As the name suggests, Windows NT 4.0 until SP6 did not boot properly unless this bit was set, but later versions of Windows do not need it, so basic leaves greater than 4 can be assumed visible on current Windows systems., basic valid leaves go up to 23h, but the information returned by some leaves are not disclosed in the publicly available documentation, i.e. they are "reserved".
Some of the more recently added leaves also have sub-leaves, which are selected via the ECX register before calling CPUID.

EAX=0: Highest Function Parameter and Manufacturer ID

This returns the CPU's manufacturer ID stringa twelve-character ASCII string stored in EBX, EDX, ECX. The highest basic calling parameter is returned in EAX.
Here is a list of processors and the highest function implemented.
The following are known processor manufacturer ID strings:

"AuthenticAMD"AMD
"CentaurHauls"IDT WinChip/Centaur
"CyrixInstead"Cyrix/early STMicroelectronics and IBM
"GenuineIntel"Intel
"GenuineIotel"Intel
"TransmetaCPU"Transmeta
"GenuineTMx86"Transmeta
"Geode by NSC"National Semiconductor
"NexGenDriven"NexGen
"RiseRiseRise"Rise
"SiS SiS SiS "SiS
"UMC UMC UMC "UMC
"Vortex86 SoC"DM&P Vortex86
"Shanghai" Zhaoxin
"HygonGenuine"Hygon
"GenuineRDC"RDC Semiconductor Co. Ltd.
"E2K MACHINE "MCST Elbrus
"VIA VIA VIA "VIA
"AMD ISBETTER"early engineering samples of AMD K5 processor

The following are ID strings used by open source soft CPU cores:

"GenuineAO486"ao486 CPU
"MiSTer AO486"ao486 CPU
"GenuineIntel"v586 core

The following are known ID strings from virtual machines:

"ConnectixCPU"Connectix Virtual PC
"Virtual CPU "Microsoft Virtual PC 7; Microsoft x86-to-ARM
"AuthenticAMD"Microsoft x86-to-ARM
"GenuineIntel"Apple Rosetta 2
"Insignia 586"Insignia RealPC and SoftWindows 98
"Compaq FX!32"Compaq FX!32
"PowerVM Lx86"PowerVM Lx86
"Neko Project"Neko Project II

For instance, on a GenuineIntel processor, values returned in EBX is 0x756e6547, EDX is 0x49656e69 and ECX is 0x6c65746e. The following example code displays the vendor ID string as well as the highest calling parameter that the CPU implements.

.intel_syntax noprefix
.text
.m0:.string "CPUID: %x\n"
.m1:.string "Largest basic function number implemented: %i\n"
.m2:.string "Vendor ID: %s\n"
.globl main
main:
push r12
mov eax, 1
sub rsp, 16
cpuid
lea rdi,.m0
mov esi, eax
call printf
xor eax, eax
cpuid
lea rdi,.m1
mov esi, eax
mov r12d, edx
mov ebp, ecx
call printf
mov 3, ebx
lea rsi, 3
lea rdi,.m2
mov 7, r12d
mov 11, ebp
call printf
add rsp, 16
pop r12
ret
.section.note.GNU-stack,"",@progbits

On some processors, it is possible to modify the Manufacturer ID string reported by CPUID. by writing a new ID string to particular MSRs using the WRMSR instruction. This has been used on non-Intel processors to enable features and optimizations that have been disabled in software for CPUs that don't return the GenuineIntel ID string. Processors that are known to possess such MSRs include:

Processor	MSRs
IDT WinChip	`108h-109h`
VIA C3, C7	`1108h-1109h`
VIA Nano	`1206h-1207h`
Transmeta Crusoe, Efficeon	`80860001h-80860003h`
AMD Geode GX, LX	`3000h-3001h`
DM&P Vortex86EX2	`52444300h-52444301h`

EAX=1: Processor Info and Feature Bits

This returns the CPU's stepping, model, and family information in register EAX, feature flags in registers EDX and ECX, and additional feature info in register EBX.

Stepping ID is a product revision number assigned due to fixed errata or other changes.
The actual processor model is derived from the Model, Extended Model ID and Family ID fields. If the Family ID field is either 6 or 15, the model is equal to the sum of the Extended Model ID field shifted left by 4 bits and the Model field. Otherwise, the model is equal to the value of the Model field.
The actual processor family is derived from the Family ID and Extended Family ID fields. If the Family ID field is equal to 15, the family is equal to the sum of the Extended Family ID and the Family ID fields. Otherwise, the family is equal to the value of the Family ID field.
The meaning of the Processor Type field is given in the table below.

Type	Encoding in Binary
Original equipment manufacturer Processor	00
Intel Overdrive Processor	01
Dual processor	10
Reserved value	11

As of October 2023, the following x86 processor family IDs are known:

Bits	EBX	Valid
7:0	Brand Index
15:8	`CLFLUSH` line size	if `CLFLUSH` feature flag is set. CPUID.01.EDX.CLFSH = 1
23:16	Maximum number of addressable IDs for logical processors in this physical package; The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package. Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.	if Hyper-threading feature flag is set. CPUID.01.EDX.HTT = 1
31:24	Local APIC ID: The initial APIC-ID is used to identify the executing logical processor.	Pentium 4 and subsequent processors.

The processor info and feature flags are manufacturer specific but usually, the Intel values are used by other manufacturers for the sake of compatibility.
Reserved fields should be masked before using them for processor identification purposes.

EAX=2: Cache and TLB Descriptor Information

This returns a list of descriptors indicating cache and TLB capabilities in EAX, EBX, ECX and EDX registers.
On processors that support this leaf, calling CPUID with EAX=2 will cause the bottom byte of EAX to be set to 01h and the remaining 15 bytes of EAX/EBX/ECX/EDX to be filled with 15 descriptors, one byte each. These descriptors provide information about the processor's caches, TLBs and prefetch. This is typically one cache or TLB per descriptor, but some descriptor-values provide other information as well - in particular, 00h is used for an empty descriptor, FFh indicates that the leaf does not contain valid cache information and that leaf 4h should be used instead, and FEh indicates that the leaf does not contain valid TLB information and that leaf 18h should be used instead. The descriptors may appear in any order.
For each of the four registers, if bit 31 is set, then the register should not be considered to contain valid descriptors
The table below provides, for known descriptor values, a condensed description of the cache or TLB indicated by that descriptor value. The suffixes used in the table are:

K,M,G : binary kilobyte, megabyte, gigabyte
E : entries
p : page-size
L : cache-line size
S : cache sector size
A : associativity

L2C/L3C:
4M, 16A, 64L