Multigate device
A multigate device, multi-gate MOSFET or multi-gate field-effect transistor refers to a metal–oxide–semiconductor field-effect transistor that has more than one gate on a single transistor. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor. The most widely used multi-gate devices are the FinFET and the GAAFET, which are non-planar transistors, or 3D transistors.
Multi-gate transistors are one of the several strategies being developed by MOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's law. Development efforts into multigate transistors have been reported by the Electrotechnical Laboratory, Toshiba, Grenoble INP, Hitachi, IBM, TSMC, UC Berkeley, Infineon Technologies, Intel, AMD, Samsung Electronics, KAIST, Freescale Semiconductor, and others, and the ITRS predicted correctly that such devices will be the cornerstone of sub-32 nm technologies. The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-κ/metal gate materials.
Dual-gate MOSFETs are commonly used in very high frequency mixers and in sensitive VHF front-end amplifiers. They are available from manufacturers such as Motorola, NXP Semiconductors, and Hitachi.
Types
Dozens of multigate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture and the number of channels/gates.Planar double-gate MOSFET (DGMOS)
A planar double-gate MOSFET employs conventional planar manufacturing processes to create double-gate MOSFET devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors the drain–source channel is sandwiched between two independently fabricated gate/gate-oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates.FlexFET
FlexFET is a planar, independently double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. FlexFET is a true double-gate transistor in that both the top and bottom gates provide transistor operation, and the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa. FlexFET was developed and is manufactured by American Semiconductor, Inc.FinFET
is a type of non-planar transistor, or "3D" transistor. The FinFET is a variation on traditional MOSFETs distinguished by the presence of a thin silicon "fin" inversion channel on top of the substrate, allowing the gate to make two points of contact: the left and right sides of the fin. The thickness of the fin determines the effective channel length of the device. The wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects.The first FinFET transistor type was called a depleted lean-channel transistor or "DELTA" transistor, which was first fabricated by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989. In the late 1990s, Digh Hisamoto began collaborating with an international team of researchers on further developing DELTA technology, including TSMC's Chenming Hu and a UC Berkeley research team including Tsu-Jae King Liu, Jeffrey Bokor, Xuejue Huang, Leland Chang, Nick Lindert, S. Ahmed, Cyrus Tabery, Yang-Kyu Choi, Pushkar Ranade, Sriram Balasubramanian, A. Agarwal and M. Ameen. In 1998, the team developed the first N-channel FinFETs and successfully fabricated devices down to a 17nm process. The following year, they developed the first P-channel FinFETs. They coined the term "FinFET" in a December 2000 paper.
In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD, IBM, and Freescale describe their double-gate development efforts as FinFET development, whereas Intel avoids using the term when describing their closely related tri-gate architecture. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one, to increase drive strength and performance. The gate may also cover the entirety of the fin.
A 25 nm transistor operating on just 0.7 volt was demonstrated in December 2002 by TSMC. The "Omega FinFET" design is named after the similarity between the Greek letter omega and the shape in which the gate wraps around the source/drain structure. It has a gate delay of just 0.39 picosecond for the N-type transistor and 0.88 ps for the P-type.
In 2004, Samsung Electronics demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory manufactured with a 90nm Bulk FinFET process. In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on FinFET technology. In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FINFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.
In 2012, Intel started using FinFETs for its future commercial devices. Leaks suggest that Intel's FinFET has an unusual shape of a triangle rather than rectangle, and it is speculated that this might be either because a triangle has a higher structural strength and can be more reliably manufactured or because a triangular prism has a higher area-to-volume ratio than a rectangular prism, thus increasing switching performance.
In September 2012, GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014. The next month, the rival company TSMC announced start early or "risk" production of 16 nm FinFETs in November 2013.
In March 2014, TSMC announced that it is nearing implementation of several 16 nm FinFETs die-on wafers manufacturing processes:
- 16 nm FinFET,
- 16 nm FinFET+,
- 16 nm FinFET "Turbo".
In March 2017, Samsung and eSilicon announced the tapeout for production of a 14 nm FinFET ASIC in a 2.5D package.
Tri-gate transistor
A tri-gate transistor, also known as a triple-gate transistor, is a type of MOSFET with a gate on three of its sides. A triple-gate transistor was first demonstrated in 1987, by a Toshiba research team including K. Hieda, Fumio Horiguchi and H. Watanabe. They realized that the fully depleted body of a narrow bulk Si-based transistor helped improve switching due to a reduced body-bias effect. In 1992, a triple-gate MOSFET was demonstrated by IBM researcher Hon-Sum Wong.Intel announced this technology in September 2002. Intel announced "triple-gate transistors" which maximize "transistor switching performance and decreases power-wasting leakage". A year later, in September 2003, AMD announced that it was working on similar technology at the International Conference on Solid State Devices and Materials. No further announcements of this technology were made until Intel's announcement in May 2011, although it was stated at IDF 2011, that they demonstrated a working SRAM chip based on this technology at IDF 2009.
On April 23, 2012, Intel released a new line of CPUs, termed Ivy Bridge, which feature tri-gate transistors. Intel has been working on its tri-gate architecture since 2002, but it took until 2011 to work out mass-production issues. The new style of transistor was described on May 4, 2011, in San Francisco. It was announced that Intel's factories were expected to make upgrades over 2011 and 2012 to be able to manufacture the Ivy Bridge CPUs. It was announced that the new transistors would also be used in Intel's Atom chips for low-powered devices.
Tri-gate fabrication was used by Intel for the non-planar transistor architecture used in Ivy Bridge, Haswell and Skylake processors. These transistors employ a single gate stacked on top of two vertical gates, allowing essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than previous transistors. This allows up to 37% higher speed or a power consumption at under 50% of the previous type of transistors used by Intel.
Intel explains: "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state, and as close to zero as possible when it is in the 'off' state, and enables the transistor to switch very quickly between the two states." Intel has stated that all products after Sandy Bridge will be based upon this design.
The term tri-gate is sometimes used generically to denote any multigate FET with three effective gates or channels.