Extensible Host Controller Interface


The eXtensible Host Controller Interface is a technical specification that provides a detailed framework for the functioning of a computer's host controller for Universal Serial Bus. Known alternately as the USB 3.0 host controller specification, xHCI is designed to be backward compatible, supporting a wide range of USB devices from older USB 1.x to the more recent USB 3.x versions.
Distinct from its predecessors, the Open Host Controller Interface, the Universal Host Controller Interface and the Enhanced Host Controller Interface, xHCI offers several technological improvements. Specifically, it is designed to handle multiple data transfer speeds within a single unified standard. This makes it more efficient in managing computational and power resources, a feature particularly beneficial for mobile devices with limited power capabilities like tablets and smartphones. Additionally, xHCI simplifies the architecture needed to support a mixture of low-speed and high-speed devices, which streamlines the development of drivers and system software.
xHCI marks a significant improvement over its predecessors, the Open Host Controller Interface, the Universal Host Controller Interface and the Enhanced Host Controller Interface, in several key ways:
  1. Multi-Speed Support: Unlike OHCI, UHCI and EHCI, which were limited to specific USB speeds, xHCI is capable of managing multiple data transfer speeds—low, full, high, and SuperSpeed—under a single standard. This eliminates the need for multiple host controllers or complex switching mechanisms when dealing with various types of USB devices, thereby improving efficiency.
  2. Power Management: xHCI includes advanced power management features that allow for selective suspension of USB devices and more granular power distribution. This is especially beneficial for mobile devices with limited battery life, such as tablets and laptops, as it helps to maximize power utilization and extend battery life.
  3. Streamlined Architecture: xHCI's architecture is designed to be simpler and more straightforward, reducing the complexity of driver development. In older architectures like OHCI, UHCI and EHCI, supporting a mix of low-speed and high-speed devices required complicated algorithms and multiple transaction translators. xHCI simplifies this by integrating these functions into the host controller itself, thus easing the burden on system software and driver developers.
By enhancing support for multiple speeds, optimizing power management, and simplifying the underlying architecture, xHCI serves as a more efficient and unified standard for USB host controllers.

Architectural goals

The xHCI is a radical break from the previous generations of USB host controller interface architectures, the Universal Host Controller Interface, and the Enhanced Host Controller Interface ) on many counts.
Following are the key goals of the xHCI architecture:
  • Efficient operation – idle power and performance better than legacy USB host controller architectures.
  • A device level programming model that is fully consistent with the existing USB software model
  • Decouple the host controller interface presented to software from the underlying USB protocols
  • Minimize host memory accesses, fully eliminating them when USB devices are idle
  • Eliminate register writes and minimize register reads for normal data transfers
  • Eliminate the "Companion Controller" model
  • Enable hardware "fail-over" modes in system resource constrained situations so devices are still accessible, but perhaps at less optimal power/performance point
  • Provide the ability for different markets to differentiate hardware capabilities, e.g. target host controller power, performance and cost trade-offs for specific markets
  • Define an extensible architecture that provides an easy path for new USB specifications and technologies, such as higher bandwidth interfaces, optical transmission medium, etc., without requiring the definition of yet another USB host controller interface

    Architectural details

Support for all speeds

The OHCI and UHCI controllers support only USB 1 speed devices, and the EHCI only supports USB 2 devices.
The xHCI architecture was designed to support all USB speeds, including SuperSpeed and future speeds, under a single driver stack.

Power efficiency

When USB was originally developed in 1995, it was targeted at desktop platforms to stem the proliferation of connectors that were appearing on PCs, e.g. PS/2, serial port, parallel port, game port, etc., and host power consumption was not an important consideration at the time. Since then, mobile platforms have become the platform of choice, and their batteries have made power consumption a key consideration. The architectures of the legacy USB host controllers were very similar in that the "schedule" for the transactions to be performed on the USB were built by software in host memory, and the host controller hardware would continuously read the schedules to determine what transactions needed to be driven on the USB, and when, even if no data was moved. Additionally, in the case of reads from the device, the device was polled each schedule interval, even if there was no data to read.
  • The xHCI eliminates host memory based USB transaction schedules, enabling zero host memory activity when there is no USB data movement.
  • The xHCI reduces the need for periodic device polling by allowing a USB 3.0 or later device to notify the host controller when it has data available to read, and moves the management of polling USB 2.0 and 1.1 devices that use interrupt transactions from the CPU-driven USB driver to the USB host controller. EHCI, OHCI, and UHCI host controllers would automatically handle polling for the CPU if there are no changes that need to be made and if no device has any interrupts to send but they all rely on the CPU to set the schedule up for the controllers. If any USB device using interrupt transactions does have data to send, then an xHCI host controller will send an interrupt to notify the CPU that there is a USB interrupt transaction that needs handling. Since the CPU no longer has to manage the polling of the USB bus, it can spend more time in low power states.
  • The xHCI does not require that implementations provide support for all advanced USB 2 and 3 power management features, including USB 2 LPM, USB 3 U1 and U2 states, HERD, LTM, Function Wake, etc.; but these features are required to realize all of the advantages of xHCI.

    Virtualization support

Legacy USB host-controller architectures exhibit some serious shortcomings when applied to virtualized environments. Legacy USB host-controller interfaces define a relatively simple hardware data-pump; where critical state related to overall bus-management resides in the software of the host-controller driver. Trying to apply the standard hardware IO virtualization technique - replicating I/O interface registers - to the legacy USB host controller interface is problematic because critical state that must be managed across virtual machines is not available to hardware. The xHCI architecture moves the control of this critical state into hardware, enabling USB resource management across VMs. The xHCI virtualization features also provide for:
  • direct-Assignment of individual USB devices to any VM
  • minimizing run-time inter-VM communications
  • support for native USB device-sharing
  • support of PCIe SR-IOV

    Simplified driver architecture

The EHCI utilizes OHCI or UHCI controllers as "companion controllers", where USB 2 devices are managed through the EHCI stack, and the port logic of the EHCI allows a low-speed or full-speed USB device to be routed to a port of a "companion" UHCI or OHCI controller, where the low-speed or full-speed USB devices are managed through the respective UHCI or OHCI stack. For example, a USB 2 PCIe host controller card that presents 4 USB "Standard A" connectors typically presents one 4-port EHCI and two 2-port OHCI controllers to system software. When a high-speed USB device is attached to any of the 4 connectors, the device is managed through one of the 4 root hub ports of the EHCI controller. If a low-speed or full-speed USB device is attached to connectors 1 or 2, it will be routed to the root hub ports of one of the OHCI controllers for management, and low-speed and full-speed USB devices attached to connectors 3 or 4 will be routed to the root hub ports of the other OHCI controller. The EHCI dependence on separate host controllers for high-speed USB devices and the group of low-speed and full-speed USB devices results in complex interactions and dependencies between the EHCI and OHCI/UHCI drivers.
  • The xHCI architecture eliminates the need for companion controllers and their separate driver stacks.
  • The incorporation of the schedule, bandwidth management, and USB device address assignment functions, that were previously performed by the driver in to the xHCI hardware enable a simpler, leaner, lower latency software stack for the xHCI.

    Stream support

Support for Streams was added to the USB 3.0 SuperSpeed specification, primarily to enable high performance storage operations over USB. Classically there has been a 1:1 relationship between a USB endpoint and a buffer in system memory, and the host controller solely responsible for directing all data transfers. Streams changed this paradigm by providing a 1-to-many "endpoint to buffer" association, and allowing the device to direct the host controller as to which buffer to move. The USB data transfers associated with a USB Stream endpoint are scheduled by the xHCI the same as any other bulk endpoint is, however the data buffer associated with a transfer is determined by the device.
  • The xHCI USB Stream support allows up to 64K buffers to be associated with a single endpoint.
  • The xHCI Streams protocol support allows a USB device to select which buffer that the xHCI will transfer when the endpoint is scheduled.