CDC 6000 series
The CDC 6000 series is a discontinued family of mainframe computers manufactured by Control Data Corporation in the 1960s. It consisted of the CDC 6200, CDC 6300, CDC 6400, CDC 6500, CDC 6600 and CDC 6700 computers, which were all extremely rapid and efficient for their time. Each is a large, solid-state, general-purpose, digital computer that performs scientific and business data processing as well as multiprogramming, multiprocessing, Remote Job Entry, time-sharing, and data management tasks under the control of the operating system called SCOPE. By 1970 there also was a time-sharing oriented operating system named KRONOS. They were part of the first generation of supercomputers. The 6600 was the flagship of Control Data's 6000 series.
Image:CDC 6600 introduced in 1964.jpg|thumb|right|CDC 6600 computer. Display console shown in the foreground, main system cabinet in background, with memory/logic/wiring to the left and middle, and power/cooling generation and control to the right.
Overview
The CDC 6000 series computers are composed of four main functional devices:- the central memory
- one or two high-speed central processors
- ten peripheral processors and
- a display console.
The family's members differ primarily by the number and kind of central processor:
- The CDC 6400 is a single CPU with an identical instruction set, but with a single unified arithmetic function unit that can only do one instruction at a time.
- The CDC 6500 is a dual-CPU system with two 6400 central processors
- The CDC 6600 is a single CPU with 10 functional units that can operate in parallel, each working on an instruction at the same time.
- The CDC 6700 is also a dual-CPU system, with a 6600 and a 6400 central processor.
- Arithmetic is ones complement.
- The name COMPASS was used by CDC for the assembly languages on both families.
- The name SCOPE was used for its operating system implementations on the 3000 and 6000 series.
History
The first member of the CDC 6000 series was the supercomputer CDC 6600, designed by Seymour Cray and James E. Thornton in Chippewa Falls, Wisconsin. It was introduced in September 1964 and performs up to three million instructions per second, three times faster than the IBM Stretch, the speed champion for the previous couple of years. It remained the fastest machine for five years until the CDC 7600 was launched. The machine is cooled by Freon refrigerant.Control Data manufactured about 100 machines of this type, selling for $6 to $10 million each.
The next system to be introduced was the CDC 6400, delivered in April 1966. The 6400 central processor is a slower, less expensive implementation with serial processing, rather than the 6600's parallel functional units. All other aspects of the 6400 are identical to the 6600. Then followed a machine with dual 6400-style central processors, the CDC 6500, designed principally by James E. Thornton, in October 1967. And finally, the CDC 6700, with both a 6600-style CPU and a 6400-style CPU, was released in October 1969.
Subsequent special edition options were custom-developed for the series, including:
- Attaching a second system configured without a Central Processor to the first; the combined total effectively was 20 peripheral and control processors with 24 channels, and the purpose was to support additional peripherals and "significantly increase the multiprogramming and batch job processing of the 6000 series."
- Control Data also marketed a CDC 6400 with a smaller number of peripheral processors:
- * CDC 6415–7 with seven peripheral processors
- * CDC 6415–8 with eight peripheral processors
- * CDC 6415–9 with nine peripheral processors
Hardware
Central memory (CM)
In all the CDC 6000 series computers, the central processor communicates with around seven simultaneously active programs, which reside in central memory. Instructions from these programs are read into the central processor registers and are executed by the central processor at scheduled intervals. The results are then returned to central memory.Information is stored in central memory in the form of words. The length of each word is 60 binary digits. The highly efficient address and data control mechanisms involved permit a word to be moved into or out of central memory in as little as 100 nanoseconds.
Extended Core Storage (ECS)
An extended core storage unit provides additional memory storage and enhances the powerful computing capabilities of the CDC 6000 series computers. The unit contains interleaved core banks, each one ECS word wide and an 488 bit buffer for each bank.While nominally slower than CM, ECS included a buffer that in some applications gave ECS better performance than CM. However, with a more common reference pattern the CM was still faster.
Central processor
The central processor is the high-speed arithmetic unit that functions as the workhorse of the computer. It performs the addition, subtraction, and logical operations and all of the multiplication, division, incrementing, indexing, and branching instructions for user programs. Note that in the CDC 6000 architecture, the central processing unit performs no input/output operations. Input/Output is totally asynchronous, and performed by peripheral processors.A 6000 series CPU contains 24 operating registers, designated X0–X7, A0–A7, and B0–B7. The eight X registers are each 60 bits long, and used for most data manipulation—both integer and floating point. The eight B registers are 18 bits long, and generally used for indexing and address storage. Register B0 is hard-wired to always return 0. By software convention, register B1 is generally set to 1. The eight 18-bit A registers are 'coupled' to their corresponding X registers: setting an address into any of registers A1 through A5 causes a memory load of the contents of that address into the corresponding X registers. Likewise, setting an address into registers A6 and A7 causes a memory store into that location in memory from X6 or X7. Registers A0 and X0 are not coupled in this way, so can be used as scratch registers. However A0 and X0 are used when addressing CDCs Extended Core Storage.
Instructions are either 15 or 30 bits long, so there can be up to four instructions per 60-bit word. A 60-bit word can contain any combination of 15-bit and 30-bit instructions that fit within the word, but a 30-bit instruction can not wrap to the next word. The op codes are six bits long. The remainder of the instruction is either three three-bit register fields, or two registers with an 18-bit immediate constant. All instructions are 'register to register'. For example, the following COMPASS code loads two values from memory, performs a 60-bit integer add, then stores the result:
SA1 X SET REGISTER A1 TO ADDRESS OF X; LOADS X1 FROM THAT ADDRESS
SA2 Y SET REGISTER A2 TO ADDRESS OF Y; LOADS X2 FROM THAT ADDRESS
IX6 X1+X2 LONG INTEGER ADD REGISTERS X1 AND X2, RESULT INTO X6
SA6 A1 SET REGISTER A6 TO ; STORES X6 TO X; THUS, X += Y
The central processor used in the CDC 6400 series contains a unified arithmetic element which performs one machine instruction at a time. Depending on instruction type, an instruction can take anywhere from five clock cycles for 18-bit integer arithmetic to as many as 68 clock cycles. The CDC 6500 is identical to the 6400, but includes two identical 6400 CPUs. Thus the CDC 6500 can nearly double the computational throughput of the machine, although the I/O throughput is still limited by the speed of external I/O devices served by the same 10 PPs/12 Channels. Many CDC customers worked on compute-bound problems.
The CDC 6600 computer, like the CDC 6400, has just one central processor. However, its central processor offers much greater efficiency. The processor is divided into 10 individual functional units, each of which was designed for a specific type of operation. All 10 functional units can operate simultaneously, each working on their own operation. The function units provided are: branch, Boolean, shift, long integer add, floating-point add, floating-point divide, two floating-point multipliers, and two increment units. Functional unit latencies are between three clock cycles for increment add and 29 clock cycles for floating-point divide.
The 6600 processor can issue a new instruction every clock cycle, assuming that various processor resources were available. These resources are tracked by a scoreboard mechanism. Also contributing to keeping the issue rate high is an instruction stack, which caches the contents of eight instruction words. Small loops can reside entirely within the stack, eliminating memory latency from instruction fetches.
Both the 6400 and 6600 CPUs have a cycle time of 100 ns. Due to the serial nature of the 6400 CPU, its exact speed is heavily dependent on instruction mix, but generally around 1 MIPS. Floating-point additions are fairly fast at 11 clock cycles, however floating-point multiplication is very slow at 57 clock cycles. Thus its floating-point speed will depend heavily on the mix of operations and can be under 200 kFLOPS. The 6600 is faster. With good compiler instruction scheduling, the machine can approach its theoretical peak of 10 MIPS. Floating-point additions take four clock cycles, and floating-point multiplications take 10 clocks The 6600 can therefore have a peak floating-point speed of 2-3 MFLOPS.
The CDC 6700 computer combines features of the other three computers. Like the CDC 6500, it has two central processors. One is a CDC 6400/CDC 6500 central processor with the unified arithmetic section; the other is the more efficient CDC 6600 central processor. The combination makes the CDC 6700 the fastest and the most powerful of the CDC 6000 series.