TI-990


The TI-990 was a series of 16-bit minicomputers sold by Texas Instruments in the 1970s and 1980s. It served as a replacement for TI's earlier minicomputer systems, the TI-960 and the TI-980. The TI-990 featured several unique innovations and was designed to be easier to program than its predecessors.
Among its core concepts was the ability to support multiprogramming using a software-switchable set of processor registers that allowed it to perform rapid context switches between programs. This was enabled through the use of register values stored in main memory that could be swapped by changing a single pointer.
TI later implemented the TI-990 in a single chip, the TMS9900, one of the first 16-bit microprocessors. Intended for use in low-end models of the TI-990, it retained the 990's memory-to-memory architecture. This chip was widely used in the TI-99/4A home computer, where details of its minicomputer-style memory model presented significant disadvantages.

Features

Workspaces

On the TI-990, registers are stored in memory and are referred to through a hardware register called the Workspace Pointer. The concept behind the workspace is that main memory was based on the new semiconductor RAM chips that TI had developed and ran at the same speed as the CPU. This meant that it didn't matter if the "registers" were real registers in the CPU or stored in memory. When the Workspace Pointer is loaded with a memory address, that address is the origin of the registers.
There are only three hardware registers in the 990: the Workspace Pointer, the Program Counter and the Status register. A context switch entailed the saving and restoring of only the hardware registers.

Extended operation

The TI-990 had a facility to allow extended operations through the use of plug in hardware. If the hardware is not present the CPU traps to allow software to perform the function. The operation code allowed for 15 attached devices on a system. Although, device 15 was reserved in TI's operating systems for the Supervisor Call, through which user programs requested I/O and other operating systems services.
On the 990/12, the XOP instruction could run microcode from the machine's Writable Control Store.

Orthogonal instruction set

The TI-990 used a fairly orthogonal instruction set. The instruction formats allowed for one, two and three word instructions. The model 990/12 CPU allowed for a four word instruction with the extended mode operations.

Architectural details

General register [addressing mode]s

Several registers had defined purposes in many instructions. These are:
  • R0 - shift counter, extended mode counter, Floating point Accumulator most significant word
  • R1 - FAC+2
  • R2 - FAC+4
  • R3 - FAC+6
  • R11 - return linkage, or pointer to operand of XOP
  • R12 - CRU base address
  • R13 - Saved Workspace Pointer
  • R14 - Saved Program Counter
  • R15 - Saved Status Register

    TI-990 instructions

The 990/4, 990/5, 990/9 instruction sets consisted of 69 instructions, the 990/10 had 72 instructions, the 990/10A had 77 instructions and the 990/12 had 144 instructions.
The instructions are grouped according to which addressing modes and how many operands they accept. A group is defined by the layout of bit-fields within the instruction word. The leftmost bits of the instruction word are sufficient to identify its group.
Group 1 instructions

The first field of the word specifies the operation to be performed, the remaining two fields provide information for locating the operands.
  • MOV
  • MOVB
  • A
  • AB
  • S
  • SB
  • C
  • CB
  • SZC
  • SZCB
  • SOC
  • SOCB
Type 2 instructions

The first field of the word specifies the operation to be performed, the second field is a relative offset to where to go, for JMP instructions, or the relative offset for CRU bit addressing.
  • JMP
  • JLT
  • JLE
  • JEQ
  • JHE
  • JGT
  • JNE
  • JNC
  • JOC
  • JNO
  • JOP
  • JL
  • JH
  • SBO
  • SBZ
  • TB
Group 3 instructions

The first field of the word specifies the operation, the second field provides the register, the third field provides information for locating the second operand.
  • COC
  • CZC
  • XOR
  • XOP
Group 4 instructions

The first field of the word specifies the operation to be performed, the second field is the bit width of the operation, the third field provides information for locating the second operand.
  • LDCR
  • STCR
Group 5 instructions

The first field of the word specifies the operation to be performed, the second field is the shift count, the third field specifies the register to shift.
  • SRA
  • SRL
  • SLA
  • SRC
Group 6 instructions

The first field specifies the operation to be performed, the second field provides information for locating the second operand.
  • BLWP
  • B
  • X
  • CLR
  • NEG
  • INV
  • INC
  • INCT
  • DEC
  • DECT
  • BL
  • ABS
  • SWPB
  • SETO
  • LDS
  • LDD
  • BIND
  • MPYS
  • DIVS
  • AR
  • CIR
  • SR
  • MR
  • DR
  • LR
  • STR
  • AD
  • CID
  • SD
  • MD
  • DD
  • LD
  • STD
Group 7 instructions

The word specified the operation to be performed.
  • IDLE
  • RSET
  • RTWP
  • CKON
  • CKOF
  • LREX
  • EMD
  • EINT
  • DINT
  • CRI
  • CDI
  • NEGR
  • NEGD
  • CRE
  • CDE
  • CER
  • CED
  • XIT
Group 8 instructions

The first field specifies the operation, the second field specifies the register if applicable. The third field, if applicable, specifies an immediate operand in a second word.
  • LIMI
  • LI
  • AI
  • ANDI
  • ORI
  • CI
  • STWP
  • STST
  • LWPI
  • BLSK
Group 9 instructions

The first field of the word specifies the operation, the second field provides the register, the third field provides information for locating the second operand.
  • MPY
  • DIV
Group 10 instruction

The first field specifies the operation, the second field specifies the map file and the third field specifies a register with an address.
The given map file is loaded with 6 words from the address in the register.
This instruction was supported on the 990/10A and 990/12, or the 990/10 with memory-map option installed.
  • LMF
Group 11 instructions

The first word is the opcode; in the second word, the first field is the byte count field, the second field is the destination operand and the third field is the source operand. These instructions are supported on the 990/12.
  • NRM
  • RTO
  • LTO
  • CNTO
  • BDC
  • DBC
  • SWPM
  • XORM
  • ORM
  • ANDM
  • SM
  • AM
The multiple precision instructions allowed for logic and integer arithmetic on operands from 1-15 bytes long. *SM and *AM were supported on the 990/10A.
Group 12 instructions

The first field of the first word is the opcode, the second field of the first word indicates a checkpoint register; the first field of the second word is the byte count field, the second field is the destination operand and the third field is the source operand. These instructions were supported on the 990/12.
  • SNEB
  • CRC
  • TS
  • CS
  • SEQB
  • MOVS
  • MVSR
  • MVSK
  • POPS
  • PSHS
Group 13 instructions

The first word is the opcode; in the second word, the first field is the byte count field, the second field is the shift count and the third field is the source operand. These instructions are supported on the 990/12 and 990/10A.
  • SRAM
  • SLAM
Group 14 instructions

The first word is the opcode; the first field of the second word is the position field and the second field is the source operand. These instructions were supported on the 990/12.
  • TMB
  • TCMB
  • TSMB
Group 15 instruction

The first field of the first word is the opcode, the second field of the first word indicates a width; the first field of the second word is the position, the second field is the source operand. This instruction supported on the 990/12.
  • IOF
Group 16 instructions

The first field of the first word is the opcode, the second field of the first word indicates a width; the first field of the second word is the position, the second field is the destination operand and the third field is the source operand. These instructions supported on the 990/12.
  • INSF
  • XV
  • XF
Group 17 instructions

The first word is the opcode; the first field of the second word is the value field and the second field is the register and the third field is the relative offset. These instructions supported on the 990/12.
  • SRJ
  • ARJ
Group 18 instructions

The first field of the word is the opcode and the second field is the register specification. These instructions supported on the 990/12.
  • STPC
  • LIM
  • LST
  • LWP
  • LCS
Group 19 instruction

The first word is the opcode; the first field of the second word is the destination operand and the second field is the source operand. This instruction supported on the 990/12.
  • MOVA
Group 20 instructions

The first word is the opcode; the first field of the second word is the condition code field, the second field is the destination operand and the third field is the source operand. These instructions supported on the 990/12.
  • SLSL
  • SLSP
Group 21 instruction

The first field of the first word is the opcode, the second field of the first word specifies the destination length; the first field of the second word specifies the source length, the second field is the destination operand and the third field is the source operand. This instruction is only supported on the 990/12.
  • EP