Sandy Bridge
Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors. The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. Intel demonstrated an A1 stepping Sandy Bridge processor in 2009 during Intel Developer Forum, and released first products based on the architecture in January 2011 under the Core brand.
Sandy Bridge is manufactured in the 32 nm process and has a soldered contact with the die and IHS, while Intel's subsequent generation Ivy Bridge uses a 22 nm die shrink and a TIM between the die and the IHS.
Technology
Upgraded features from Nehalem include:CPU
- Intel Turbo Boost 2.0
- 32 KB data + 32 KB instruction L1 cache and 256 KB L2 cache per core
- Shared L3 cache which includes the processor graphics
- 64-byte cache line size
- New μOP cache, up to 1536-entry
- Improved 3 integer ALU, 2 vector ALU and 2 AGU per core
- Two load/store operations per CPU cycle for each memory channel
- Decoded micro-operation cache, and enlarged, optimized branch predictor
- Sandy Bridge retains the four branch predictors found in Nehalem: the branch target buffer, indirect branch target array, loop detector and renamed return stack buffer. Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem.
- Improved performance for transcendental mathematics, AES encryption, and SHA-1 hashing
- 256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain
- Advanced Vector Extensions 256-bit instruction set with wider vectors, new extensible syntax and rich functionality
- Up to 8 physical cores, or 16 logical cores through hyper-threading
- Integration of the GMCH and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor, Clarkdale, has two separate dies within the processor package. This tighter integration reduces memory latency even more.
- A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss
- Increased ROB to 168 entries
- Larger Scheduler buffer
GPU
- Intel Quick Sync Video, hardware support for video encoding and decoding
- Integrated graphics is now integrated on the same die
- OpenGL 3.3 support
I/O
- Integrated PCIe Controller
Models and steppings
0206D6h and 0206D7h. Ivy Bridge CPUs all have CPUID 0306A9h to date, and are built in four different configurations differing in the number of cores, L3 cache and GPU execution units:| Die codename | CPUID | Stepping | Cores | GPU EUs | L3 cache | Socket |
| Sandy Bridge-HE-4 | 0206A7h | D2 | 4 | 12 | 8 MB | LGA 1155, Socket G2, BGA-1023, BGA-1224 |
| Sandy Bridge-H-2 | 0206A7h | J1 | 2 | 12 | 4 MB | LGA 1155, Socket G2, BGA-1023 |
| Sandy Bridge-M-2 | 0206A7h | Q0 | 2 | 6 | 3 MB | LGA 1155, Socket G2, BGA-1023 |
| Sandy Bridge-EP-8 | 0206D6h | C1 | 8 | none | 20 MB | LGA 2011 |
| Sandy Bridge-EP-8 | 0206D7h | C2 | 8 | none | 20 MB | LGA 2011 |
| Sandy Bridge-EP-4 | 0206D6h | M0 | 4 | none | 10 MB | LGA 2011 |
| Sandy Bridge-EP-4 | 0206D7h | M1 | 4 | none | 10 MB | LGA 2011 |
Performance
- The average performance increase, according to IXBT Labs and Semi Accurate as well as many other benchmarking sites, at clock to clock is 11.3% compared to the Nehalem generation, which includes Bloomfield, Clarkdale, and Lynnfield processors.
- Around twice the integrated graphics performance compared to Clarkdale's.
List of Sandy Bridge processors
- This list may not contain all the Sandy Bridge processors released by Intel. A more complete listing can be found on Intel's website.
Desktop platform
- K – Unlocked
- P – Versions clocked slightly higher than similar models, but with onboard-graphics deactivated
- S – Performance-optimized lifestyle
- T – Power-optimized lifestyle
- X – Extreme performance and unlocked
- C – Embedded/Communications - BGA packaging
Server platform
All 1600/2600/4600-series models:- support 40 PCI Express 3.0 lanes
- support DMI 2.0
- support LGA 2011 as a socket with varying scalabilities
- L – Low power
- W – Optimized for workstations
Mobile platform
- Core i5-2515E and Core i7-2715QE processors have support for ECC memory and PCI express port bifurcation.
- All mobile processors, except Celeron and Pentium, use the HD 3000 iGPU.
- M – Mobile processors
- * UM – Ultra low power mobile
- * LM – Low power mobile
- * M – Dual-core mobile
- * QM – Quad-core mobile
- * XM – Quad-core extreme mobile
- E – Embedded mobile processors
- * QE – Quad-core
- * LE – Low power
- * UE – Ultra low power
Cougar Point chipset flaw
Intel stopped production of flawed B2 stepping chipsets and began producing B3 stepping chipsets with the silicon fix. Shipping of these new chipsets started on 14 February 2011 and Intel estimated full recovery volume in April 2011. Motherboard manufacturers and computer manufacturers stopped selling products that involved the flawed chipset and offered support for affected customers. Options ranged from swapping for B3 motherboards to product refunds.
Sandy Bridge processor sales were temporarily on hold, as one cannot use the CPU without a motherboard. However, processor release dates were not affected. After two weeks, Intel continued shipping some chipsets, but manufacturers had to agree to a set of terms that will prevent customers from encountering the bug.
Limitations
Overclocking
With Sandy Bridge, Intel has tied the speed of every bus to a single internal clock generator issuing the basic Base Clock. With CPUs being multiplier locked, the only way to overclock is to increase the BClk, which can be raised by only 5–7% without other hardware components failing. As a work around, Intel made available K/X-series processors, which feature unlocked multipliers; with a multiplier cap of 57 for Sandy Bridge. For the Sandy Bridge-E platform, there is alternative method known as the BClk ratio overclock.During IDF 2010, Intel demonstrated an unknown Sandy Bridge CPU running stably overclocked at 4.9 GHz on air cooling.