Integrating ADC
An integrating ADC is a type of analog-to-digital converter that converts an unknown input voltage into a digital representation through the use of an integrator. In its basic implementation, the dual-slope converter, the unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed time period. Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero. The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period. The run-down time measurement is usually made in units of the converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed of the converter can be improved by sacrificing resolution.
Converters of this type can achieve high resolution, but often do so at the expense of speed. For this reason, these converters are not found in audio or signal processing applications. Their use is typically limited to digital voltmeters and other instruments requiring highly accurate measurements.
Basic design: Dual-Slope ADC
The basic integrating ADC circuit consists of an integrator, a switch to select between the voltage to be measured and the reference voltage, a timer that determines how long to integrate the unknown and measures how long the reference integration took, a comparator to detect zero crossing, and a controller. Depending on the implementation, a switch may also be present in parallel with the integrator capacitor to allow the integrator to be reset. Inputs to the controller include a clock and the output of a comparator used to detect when the integrator's output reaches zero.The conversion takes place in two phases: the run-up phase, where the input to the integrator is the voltage to be measured, and the run-down phase, where the input to the integrator is a known reference voltage. During the run-up phase, the switch selects the measured voltage as the input to the integrator. The integrator is allowed to ramp for a fixed period of time to allow a charge to build on the integrator capacitor. During the run-down phase, the switch selects the reference voltage as the input to the integrator. The time that it takes for the integrator's output to return to zero is measured during this phase.
In order for the reference voltage to ramp the integrator voltage down, the reference voltage needs to have a polarity opposite to that of the input voltage. In most cases, for positive input voltages, this means that the reference voltage will be negative. To handle both positive and negative input voltages, a positive and negative reference voltage is required. The selection of which reference to use during the run-down phase would be based on the polarity of the integrator output at the end of the run-up phase.
Image:dual slope integrator graph.svg|frame|Integrator output voltage in a basic dual-slope integrating ADC
The basic equation for the output of the integrator is:
Assuming that the initial integrator voltage at the start of each conversion is zero and that the integrator voltage at the end of the run down period will be zero, we have the following two equations that cover the integrator's output during the two phases of the conversion:
The two equations can be combined and solved for, the unknown input voltage:
From the equation, one of the benefits of the dual-slope integrating ADC becomes apparent: the measurement is independent of the values of the circuit elements. This does not mean, however, that the values of R and C are unimportant in the design of a dual-slope integrating ADC.
Note that in the graph, the voltage is shown as going up during the run-up phase and down during the run-down phase. In reality, because the integrator uses the op-amp in a negative feedback configuration, applying a positive will cause the output of the integrator to go down. The up and down more accurately refer to the process of adding charge to the integrator capacitor during the run-up phase and removing charge during the run-down phase.
The resolution of the dual-slope integrating ADC is determined primarily by the length of the run-down period and by the time measurement resolution. The required resolution dictates the minimum length of the run-down period for a full-scale input :
During the measurement of a full-scale input, the slope of the integrator's output will be the same during the run-up and run-down phases. This also implies that the time of the run-up period and run-down period will be equal and that the total measurement time will be. Therefore, the total measurement time for a full-scale input will be based on the desired resolution and the frequency of the controller's clock:
Typically the run-up time is chosen to be a multiple of the period of the mains frequency, to suppress mains hum.
Limitations
There are limits to the maximum resolution of the dual-slope integrating ADC. It is not possible to increase the resolution of the basic dual-slope ADC to arbitrarily high values by using longer measurement times or faster clocks. Resolution is limited by:- The range of the integrating amplifier. The voltage rails on an op-amp limit the output voltage of the integrator. An input left connected to the integrator for too long will eventually cause the op amp to limit its output to some maximum value, making any calculation based on the run-down time meaningless. The integrator's resistor and capacitor are therefore chosen carefully based on the voltage rails of the op-amp, the reference voltage and expected full-scale input, and the longest run-up time needed to achieve the desired resolution.
- The accuracy of the comparator used as the null detector. Wideband circuit noise limits the ability of the comparator to identify exactly when the output of the integrator has reached zero. Goeke suggests a typical limit is a comparator resolution of 1 millivolt.
- The quality of the integrator's capacitor. Although the integrating capacitor need not be perfectly linear, it does need to be time-invariant. Dielectric absorption causes linearity errors.
Enhancements
Run-up improvements
Enhanced dual-slope
The run-up phase of the basic dual-slope design integrates the input voltage for a fixed period of time. That is, it allows an unknown amount of charge to build up on the integrator's capacitor. The run-down phase is then used to measure this unknown charge to determine the unknown voltage. For a full-scale input equal to the reference voltage, half of the measurement time is spent in the run-up phase. Reducing the amount of time spent in the run-up phase can reduce the total measurement time. A common implementation uses an input range twice as large as the reference voltage.A simple way to reduce the run-up time is to increase the rate that charge accumulates on the integrator capacitor by reducing the size of the resistor used on the input. This still allows the same total amount of charge accumulation, but it does so over a smaller period of time. Using the same algorithm for the run-down phase results in the following equation for the calculation of the unknown input voltage :
Note that this equation, unlike the equation for the basic dual-slope converter, has a dependence on the values of the integrator resistors. Or, more importantly, it has a dependence on the ratio of the two resistance values. This modification does nothing to improve the resolution of the converter.
Multi-slope run-up
The purpose of the run-up phase is to add a charge proportional to the input voltage to the integrator to be later measured during the run-down phase. One method to improve the resolution of the converter is to artificially increase the range of the integrating amplifier during the run-up phase.One method to increase the integrator capacity is by periodically adding or subtracting known quantities of charge during the run-up phase in order to keep the integrator's output within the range of the integrator amplifier. The total accumulated charge is the charge introduced by the unknown input voltage plus the sum of the known charges that were added or subtracted.
The circuit diagram shown to the right is an example of how multi-slope run-up could be implemented. During the run-up the unknown input voltage,, is always applied to the integrator. Positive and negative reference voltages controlled by the two independent switches add and subtract charge as needed to keep the output of the integrator within its limits. The reference resistors, and are necessarily smaller than to ensure that the references can overcome the charge introduced by the input. A comparator connected to the integrator's output is used to decide which reference voltage should be applied. This can be a relatively simple algorithm: if the integrator's output above the threshold, enable the positive reference ; if the integrator's output is below the threshold, enable the negative reference. The controller keeps track of how often each switch is turned on in order to account for the additional charge placed onto the integrator capacitor as a result of the reference voltages.
The charge added / subtracted during the multi-slope run-up form the coarse part of the result.
Image:multislope runup integrator graph.svg|frame|Output from multi-slope run-up
To the right is a graph of sample output from the integrator during such a multi-slope run-up. Each dashed vertical line represents a decision point by the controller where it samples the polarity of the output and chooses to apply either the positive or negative reference voltage to the input. Ideally, the output voltage of the integrator at the end of the run-up period can be represented by the following equation:
where is the sampling period, is the number of periods in which the positive reference is switched in, is the number of periods in which the negative reference is switched in, and is the total number of periods in the run-up phase.
The resolution obtained during the run-up is given by the number of periods of the run-up algorithm. The multi-slope run-up comes with multiple advantages:
- As the analog stored charge is much smaller, the integration capacitor can be smaller and thus a higher voltage is present at the integrator output for the same charge. This make the comparator noise less critical and smaller charges can be resolved.
- With less charge stored in the capacitor the dielectric absorption has less effect. This reduces a major source of linearity error for the dual-slope ADC.
- With less charge the run-down can be quite fast. Part of the result is already obtained during the run-up.
- The length of the run-up phase can be varied with no problem, just by changing the number of cycles in the run-up algorithm. So the same hardware can be used for fast conversion with reduced resolution or slow conversions with high resolution. The dual slope ADC is less flexible, with ideally an integration capacitor proportional to the integration time to make full use of the integrator's output swing.
Some of this error can be reduced by careful operation of the switches. In particular, during the run-up period, each switch should be activated a constant number of times. The algorithm explained above does not do this and just toggles switches as needed to keep the integrator output within the limits. Activating each switch a constant number of times makes the error related to switching approximately constant. Any output offset that is a result of the switching error can be measured and then numerically subtracted from the result.