Zen 5
Zen 5 is a microarchitecture for CPUs by AMD, shown on their roadmap in May 2022, launched for mobile in July 2024 and for desktop in August 2024. It is the successor to Zen 4 and is currently fabricated on TSMC's N4P process. Zen 5 is also planned to be fabricated on the N3E process in the future.
The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors, Epyc 9005 server processors, and Ryzen AI 300 thin and light mobile processors.
Background
Zen 5 was first officially mentioned during AMD's Ryzen Processors: One Year Later presentation on April 9, 2018.A roadmap shown during AMD's Financial Analyst Day on June 9, 2022 confirmed that Zen 5 and Zen 5c would be launching in 3 nm and 4 nm variants in 2024. The earliest details on the Zen 5 architecture promised a "re-pipelined front end and wide issue" with "integrated AI and Machine Learning optimizations".
During AMD's Q4 2023 earnings call on January 30, 2024, AMD CEO Lisa Su stated that Zen 5 products would be "coming in the second half of the year".
Architecture
Zen 5 is a ground-up redesign of Zen 4 with a wider front-end, increased floating-point throughput, and more-accurate branch prediction.Fabrication process
Zen 5 was designed with both 4 nm and 3 nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues, or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%. Additionally, Apple, as TSMC's largest customer, gets priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue. After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs. Zen 5 desktop and server processors continue to use the N6 node for the I/O die fabrication.Zen 5 Core Complex Dies are fabricated on TSMC's N4X node which is intended to accommodate higher frequencies for high-performance computing applications. Zen 4-based mobile processors were fabricated on the N4P node which is targeted more toward power efficiency. N4X maintains IP compatibility with N4P and offers a 6% frequency gain over N4P at the same power but comes with the trade-off of moderate leakage. Compared to the N5 node used to produce Zen 4 CCDs, N4X can enable up to 15% higher frequencies while running at 1.2V.
The Zen 5 CCD, codenamed "Eldora", has a die size of 70.6mm2, a 0.5% reduction in area from Zen 4's 71mm2 CCD while achieving a 28% increase in transistor density due to the N4X process node. Zen 5's CCD contains 8.315 billion transistors compared to the Zen 4 CCD's 6.5 billion transistors. One Zen 5 core is larger than one Zen 4 core, but the CCD has been reduced via shrinking the L3 cache. The monolithic die used by "Strix Point" mobile processors, fabricated on TSMC's lower power N4P node, measures 232.5mm2 in area.
Front end
Branch prediction
Zen 5's changes to branch prediction are the most significant divergence from any previous Zen microarchitecture. The branch predictor in a core tries to predict the outcome when there are diverging code paths.Zen 5's branch predictor is able to operate two-ahead where it can predict up to two branches per clock cycle. Previous architectures were limited to one branch instruction per clock cycle, limiting the instruction-fetch throughput of branch-heavy programs. Two-ahead branch predictors have been discussed in academic research dating back to André Seznec et al.'s 1996 paper "Multiple-block ahead branch predictors". 28 years after it was first proposed in academic research, AMD's Zen 5 architecture became the first microarchitecture to fully implement two-ahead branch prediction. Increased data prefetching assists the branch predictor.
Execution engines
Integer units
Zen 5 contains six Arithmetic Logic Units, up from four ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.Vector engines and instructions
The vector engine in Zen 5 features four floating-point pipes compared to three pipes in Zen 4. Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating-point pipe width to a native 512-bit floating-point datapath. The AVX-512 datapath is configurable depending on the product. Ryzen 9000 series desktop processors and EPYC 9005 server processors feature the full 512-bit datapath, but Ryzen AI 300 mobile processors feature a 256-bit datapath to reduce power consumption. AVX-512 instruction has been extended to VNNI/VEX instructions. Additionally, there is greaterbfloat16 throughput.Cache
L1
The wider front end in the Zen 5 architecture necessitates larger caches and higher memory bandwidth in order to keep the cores fed with data. The L1 cache per core is increased from 64 KB to 80 KB per core. The L1 instruction cache remains the same at 32 KB but the L1 data cache is increased from 32 KB to 48 KB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating-point unit pipes has also been doubled. The L1 data cache's associativity has increased from 8-way to 12-way in order to accommodate its larger size.L2
The L2 cache remains at 1 MB but its associativity has increased from 8-way to 16-way. Zen 5 also has a doubled L2 cache bandwidth of 64 bytes per clock.L3
The L3 cache is filled from L2 cache victims and in-flight misses. Latency for accessing the L3 cache has been reduced by 3.5 cycles. A Zen 5 Core Complex Die contains 32 MB of L3 cache shared between the 8 cores. In Zen 5 3D V-Cache CCDs, a piece of silicon containing 64 MB of extra L3 cache is placed under the cores rather than on top like in prior generations for a total of 96 MB. This allows for increased core frequency compared to previous generation 3D V-Cache implementations which were sensitive to higher voltages. The Zen 5-based Ryzen 7 9800X3D has a 500 MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time.Ryzen AI 300 APUs, codenamed "Strix Point", features 24 MB of total L3 cache which is split into two separate cache arrays. 16 MB of dedicated L3 cache is shared by the 4 Zen 5 cores and 8 MB is shared by the 8 Zen 5c cores. Zen 5c cores are not able to access the 16 MB L3 cache array and vice versa.
Other changes
Other features and changes in the Zen 5 architecture, compared to Zen 4, include:- Memory speeds up to DDR5-5600 and LPDDR5X-7500 are officially supported.
| Attribute | Zen 4 | Zen 5 |
| L1/L2 BTB | 1.5K/7K | 16K/8K |
| Return Address Stack | 32 | 52 |
| ITLB L1/L2 | 64/512 | 64/2048 |
| Fetched/Decoded Instruction Bytes/cycle | 32 | 64 |
| Op Cache associativity | 12-way | 16-way |
| Op Cache bandwidth | 9 macro-ops | 12 inst or fused inst |
| Dispatch bandwidth | 6 | 8 |
| AGU Scheduler | 3x24 ALU/AGU | 56 |
| ALU Scheduler | 1x24 ALU | 88 |
| ALU/AGU | 4/3 | 6/4 |
| Int PRF | 224/126 | 240/192 |
| Vector Reg | 192 | 384 |
| FP Pre-Sched Queue | 64 | 96 |
| FP Scheduler | 2x32 | 3x38 |
| FP Pipes | 3 | 4 |
| Vector Width | 256 | 256b/512b |
| ROB/Retire Queue | 320 | 448 |
| LS Mem Pipes support Load/Store | 3/1 | 4/2 |
| DTLB L1/L2 | 72/3072 | 96/4096 |
Products
Desktop
Granite Ridge
AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4 nm process, the processors feature between 6 and 16 cores. Ryzen 9000 processors were released in August 2024.In May 2025 four of these processors were also released in the 4005 range of the EPYC brand, with the 4585PX corresponding to the 9950X3D, the 4565P to the 9950X, the 4345P to the 9700X, and the 4245P to the 9600. Two EPYC 4005 parts, both 65W, have no direct Ryzen 9000 series equivalent: the EPYC 4465P with 12 cores at 3.4 GHz, and the 4545P with sixteen cores at 3.0 GHz.
Shimada Peak
AMD announced the Threadripper 9000 series of high-end desktop processors at Computex 2025, which released on July 30, 2025. These processors succeed the Zen 4 "Storm Peak" lineup and feature up to 96 Zen 5 cores. The processors come in two variants—the consumer "Threadripper" models and the more expensive workstation "Threadripper PRO" variants, which support more memory channels and PCIe lanes.Threadripper 9000 processors officially support up to 6400 MT/s DDR5 memory, a significant increase from 5200 MT/s in the previous generation.