GE 645

The GE 645 mainframe computer was a development of the GE 635 for use in the Multics project. This was the first computer that implemented a configurable hardware protected memory system. It was designed to satisfy the requirements of Project MAC to develop a platform that would host their proposed next generation time-sharing operating system and to meet the requirements of a theorized computer utility. The system was the first truly symmetric multiprocessing machine to use virtual memory, and it was also among the first machines to implement what is now known as a translation lookaside buffer, the foundational patent for which was granted to John Couleur and Edward Glaser.
General Electric initially publicly announced the GE 645 at the Fall Joint Computer Conference in November 1965. At a subsequent press conference in December of that year it was announced that they would be working towards "broad commercial availability" of the system. However they would subsequently withdraw it from active marketing at the end of 1966. In total at least 6 sites ran GE 645 systems in the period from 1967 to 1975.

System configuration

The basic system configuration consisted of a combination of 4 basic modules these were:

Processor
System Controller
Generalized I/O Controller
Extended Memory Unit

The System Controller Modules effectively acted as the heart of the system. These were passive devices which was connected to each active device and provided the following:

Core Memory - 1 microsecond memory in size capacities of 32K, 64K or 128K of 36-bit words.
Centralized point for forwarding control signals from one active module to another
System Clock and the ability to issue interrupts to the processors.

Compared to the rest of the 600 series the 645 did not use the standard IOC's for I/O. Nor did it use the DATANET-30 front end processor for communications. Instead both sets of functionality was combined into one unit called a GIOC which provided dedicated channels for both Peripheral and Terminal I/O. The GIOC acted as an Active Device and was directly connected to memory via dedicated links to each System Controller that was present in a specific configuration.
The Extended Memory Unit, though termed a drum, was in reality a large fixed-head hard disk with one head per track, this was a OEM product from Librascope. The EMU consisted of 4,096 tracks providing 4MW of storage. Each track had a dedicated read/write head, these were organised into groups of 16 "track sets" which are used to read/write a sector. A sector is the default unit of data allocation in the EMU and is made up of 80 words, of which 64 words are data and the remaining 16 were used as a guard band. The average transfer rate between the EMU and memory was 470,000 words per second, all transfers were 72-bits wide, with it taking 6.7μs to transfer 4 words. The unit had a rotational speed of 1,725 rpm, which ensured an average latency of 17.4 milliseconds.

Component	Small	Typical	Large
System Configuration Console	1	1	2
Processor	1	2	4
GIOC	1	2	3
System Controllers Total Capacity	2 128K	4 256K	8 1024K
Extended Memory Unit Total capacity	1 4096K	1 4096K	1 4096K
Fixed disc	33M	67M	134M
Magnetic Cards	--	113M	226M
Magnetic tape handlers	4	16	32
Printers	2	4	6
Card Readers	1	2	3
Card Punches	1	2	2
Perforated Tape	--	1	2
Channels for TTY's	64	192	384
Channels for voice-grade communication lines for remote terminals such as such as DATANET-760 / GE-115	--	12	18

Architecture

Processor Modes

The GE-645 has two modes of Instruction Execution inherited from the GE-635, however it also adds another dimension by having two modes of memory addressing. When the process is executing in Absolute Mode addressing is limited to 2¹⁸ words of memory and any instructions are executed in Master mode. In comparison Append Mode calculates the address using "Appending Words" with an address space of 2²⁴ words and with instruction execution occurring in either Master or Slave modes.

Slave Mode

By default this is normal mode that the processor should be executing in at any point in time. Nearly all instructions will run in this mode aside from a small set of privileged instructions which cannot execute in this mode. Execution of such instructions will trigger an illegal procedure fault, also the ability to inhibit interrupts is forbidden. Format of instruction addresses is via the Appending Process.

Master Mode

In this mode the processor can execute all instructions and is able to inhibit interrupts while doing so. Like in Slave mode the default form of address formation is via the Appending Process.

Absolute Mode

All instructions can be executed in this mode and full access is given to any privileged features of the hardware. Interrupts can be inhibited and instruction fetching is limited to a 2¹⁸ absolute address thus restricting the processor to only been able to access the lower 256 KW of physical core memory. The processor will switch to this mode in the event of a fault or interrupt and will remain in it until it executes transfer instruction whose operand address has been obtained via the appending process.

Appending Mode

By default this is normal mode of Memory addressing, both Master and Slave modes normally operate in this mode. Indirect words and operands are accessed via Appending Mechanism via the process of placing a 1 in bit 29 of the executed instruction. Effective addresses are thus either added to a base address, or the offset is linked to the base address.

Functional Units

The 645 processor was divided into four major functional units these were:

Appending Unit:
* Controls data I/O from memory
* Controls memory selection and interleave
* Carries out Memory appending
* Control fault recognition
* Does power on/off sequencing
Associative Memory Unit:
* Consists of Associative Memory made up of 16 x 60-bit Registers
* Registers point to most recently used segment or most recently used Page
* Performs the function of what would now be classed as a TLB.
Control Unit:
* Performs all control functions
* Performs Address modification
* Controls the processor mode
* Interrupt recognition/handling
* Opcode decoding
Operations Unit:
* Performs fractional and integer divisions and multiplications.
* Performs automatic alignment of floating-point numbers for addition and subtraction.
* Performs inverted divisions on floating-point numbers.
* Performs automatic normalization of floating-point resultants.
* Performs shifts.
* Performs indicator register loading and storing.
* Performs timer register loading and decrementing.

One of the key differences from the GE 635 was the addition of "appending unit" which was used to implement a hybrid "Paged Segmentation" model of virtual memory. The APU was also used to implement a single-level store which is one of the fundamental abstraction that Multics is built around. The instruction format was also extended with the previously unused bit 29 controlling whether the operand address of an instruction used an 18-bit format or one that was made up of a 3-bit Base Register address with a 15-bit offset.
The instruction format with bit 29 set to 1 is:


 1 1 2 2 2 2 3 3
 0 2 3 7 8 6 7 8 9 0 5
 +---+---------------+---------+-+-+-+------+
 |BR | Y | OP |0|I|1| Tag |
 +---+---------------+---------+-+-+-+------+

B is the base register field
Y is the address field, addressing 32KW
OP is the opcode, the additional bit 27 is the opcode extension bit.
I is the interrupt inhibit bit.
Tag indicates the type of address modification to be performed; some additional tags are supported by the GE 645.
Address base registers

The GE 645 had 8 Address Base Registers, these could operate in either "paired" or "unpaired" modes. The later Honeywell 6180 changed these to 8 pointer registers. Each abr was 24-bits wide consisting of 18 bits for an address and 6 bits for control functions.
One bit of the control functions field indicates where an abr is "internal" or "external". If an abr is internal, another 3-bit subfield of the control functions field specifies another abr with which this abr is paired; that other abr is external, with the external abr containing a segment number in the address field and the internal abr containing an offset within the segment specified by the external abr. If an instruction or an indirect word refers to an external abr, the address field in the instruction or indirect word is used as an offset in the segment specified by the external abr. If it refers to an internal abr, the address field in the instruction or indirect word is added to the offset in the abr, and the resulting value is used as an offset in the segment specified by the external abr with which the internal abr is paired.
The registers have the following formats depending on how bit 21 is set.
Format as an "external" base, with bit 21 set:


 1 1 2 2 22 
 0 7 8 0 1 23 
 +------------------+---+-+--+
 | PDW |\\\|1|\\|
 +------------------+---+-+--+

Format as a component to the effective "internal" address with a pointer to an "external" base, with bit 21 clear:


 1 1 2 2 22 
 0 7 8 0 1 23 
 +------------------+---+-+--+
 | PY |PB |0|\\|
 +------------------+---+-+--+

PDW is the Pointer to a descriptor word
PY is the component P of the effective internal address 'Y'
PB is pointer to another base register whose bit 21 = 1

In Multics, an even-numbered abr and the following odd-numbered abr were paired. When writing in Assembly the standard Multics practice was to label these registers as follows:

ap for abr 0
ab for abr 1
bp for abr 2
bb for abr 3
lp for abr 4
lb for abr 5
sp for abr 6
sb for abr 7

The naming scheme is based around the following:

a for argument-list pointer
b for general base
l for linkage-segment pointer
s for stack-segment pointer

The 8 pointer registers in the Honeywell 6180 and its successors served the same purpose as the 4 paired base registers in the GE-645, referring to an offset within a segment.