COP8


The National Semiconductor COP8 is an 8-bit CISC core microcontroller. COP8 is an enhancement to the earlier COP400 4-bit microcontroller family. COP8 main features are:
The COP8 has a basic instruction cycle time 1/10 of the clock frequency; a maximum 10 MHz clock will result in a maximum 1 MHz instruction execution rate. The maximum instruction execution rate is 1 cycle per byte, and most 1-byte instructions operate in one instruction cycle. Some, particularly branch instructions, take one or two cycles more. Some models include a clock doubler, and although they still accept a maximum 10 MHz input clock, they internally double it to a 20 MHz master clock which then results in a 2 MHz instruction execution rate.
The chip is a static logic design which can tolerate an arbitrarily slow clock; most models include a second quartz clock crystal oscillator which can be used for the CPU clock while the high-speed clock is disabled to save power.

Registers and memory map

The COP8 uses separate instruction and data spaces. Instruction address space is 15-bit, while data addresses are 8-bit.
To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction. Invalid RAM above the stack reads as all-ones, which is an invalid address.
The CPU has an 8-bit accumulator and 15-bit program counter. 16 additional 8-bit registers and an 8-bit program status word are memory mapped. There are special instructions to access them, but general RAM access instructions may also be used.
The memory map is divided into half RAM and half control registers as follows:
AddressesUse
0x00–6FGeneral purpose RAM, used for stack
0x70–7FUnused, reads as all-ones to trap stack underflows
0x80–8FUnused, reads undefined
0x90–BFAdditional peripheral control registers
0xC0–CFPeripheral control registers.
0xD0–DFGeneral purpose I/O ports L, G, I, C and D
0xE0–E8Reserved
0xE9Microwire shift register
0xEA–EDTimer 1 registers
0xEECNTRL register, control bits for Microwire & Timer 1
0xEFPSW, CPU program status word
0xF0–FBR0–R11, on-chip RAM mapped as registers
0xFCR12, a.k.a. X, secondary indirect pointer register
0xFDR13, a.k.a. SP, stack pointer register
0xFER14, a.k.a. B, primary indirect pointer register
0xFFR15, a.k.a. S, data segment extension register

If RAM is not banked, then R15 is just another general-purpose register. If RAM is banked, then the low half of the data address space is directed to a RAM bank selected by S. The special purpose registers in the high half of the data address space are always visible. The data registers at 0xFx can be used to copy data between banks.
RAM banks other than bank 0 have all 128 bytes available. The stack is always on bank 0, no matter how the S register is set.

Control transfers

In addition to 3-byte and instructions which can address the entire address space, 2-byte versions of these instructions, and, can jump within a 4K page. The instruction specifies the low 12 bits, and the high 3 bits of the PC are preserved. For short-distance branches, there are 63 1-byte instructions,, which perform PC-relative branches from PC−32 to PC+31. This is a 15-bit addition, and no page boundary requirements apply.
There are also jump indirect and load accumulator indirect instructions which use the accumulator contents as the low 8 bits of an address; the high 7 bits of the current PC are preserved.
Conditional branches per se do not exist, nor does the processor provide the traditional ZCVN status flags, although the program status word contains carry and half-carry flags for multi-byte arithmetic. Rather, there are a number of compare-and-skip instructions. For example, compares its two operands, and skips the following instruction if they are unequal. Any instruction may be skipped; it is not limited to branches.
An interesting extension of this mechanism is the return-and-skip instruction, which lets any subroutine conditionally skip the instruction following the call. This provides a very compact way to return a boolean value from a subroutine.
Another feature unique to the COP8 architecture is the instruction. This one-byte instruction compares the low 4 bits of the B register with a 4-bit immediate constant, and can be used to loop until B has reached the end of a small buffer. There is also a one-byte instruction.

Instruction set

COP8 operands are listed in destination, source order. Most instructions have the accumulator A as one of the operands. The other operand is generally chosen from an 8-bit immediate value, an 8-bit RAM address, or, the RAM address selected by the B register. The and instructions also support RAM addressing by the X register and post-inc/decrement variants.
Indirect addressing via B is particularly fast, and can be done in the same cycle that the instruction is executed; even is a one-cycle instruction.
On the other hand, absolute RAM addressing is only directly encoded for five instructions: LD A,addr8, X A,addr8, IFEQ addr8,#imm8, LD addr8,#imm8, and DIR addr8. The latter is a "direct addressing" opcode prefix which may be prepended to any instruction with a operand, and changes the operand to the specified memory location. Using with the, and LD ,#imm8 instructions is not documented, as the dedicated instructions are more efficient.
All "move" instructions are called even if the destination is a memory address. Unusually, there are no instructions with the accumulator as a source; stores must be done with the instruction which exchanges the accumulator with the memory operand, storing A and loading the previous memory contents.
There are instructions to fetch from tables in ROM. These combine the high 7 bits of the program counter with the accumulator, fetch a byte from that address, and place it in the accumulator or the low 8 bits of the program counter PCL. Because the next instruction executed must be in the same 256-byte page of ROM as the table itself, a 256-entry table is not possible.

Notable uses